Inventor · disambiguated record
Jeffrey Chee
Also filed as: CHEE JEFFREY · CHEE JEFFREY JOCK FAI
15 granted patents·2 pending applications·63 citations·filing 1982–2019
90Inventor score
Files withGLOBALFOUNDRIES INC5CHARTERED SEMICONDUCTOR MFG3GLOBALFOUNDRIES SG PTE LTD3TEO LEE WEE2CHEE JEFFREY1
Top patents by PatentIndex Score
17 records- 0194US10446483B2Metal-insulator-metal capacitors with enlarged contact areasGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 15, 2019·12 cites·20 claims
- 0287US10825811B2Gate cut first isolation formation with contact forming process mask protectionGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 3, 2020·4 cites·18 claims
- 0377US11037821B2Multiple patterning with self-alignment provided by spacersGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 15, 2021·2 cites·13 claims
- 0469US8716081B2Capacitor top plate over source/drain to form a 1T memory deviceTEO LEE WEE·Filed 2007·Granted May 6, 2014·4 cites·29 claims
- 0569US8274115B2Hybrid orientation substrate with stress layerTEO LEE WEE·Filed 2008·Granted Sep 25, 2012·4 cites·16 claims
- 0666US8053327B2Method of manufacture of an integrated circuit system with self-aligned isolation structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Nov 8, 2011·3 cites·10 claims
- 0760US6099928AMultipurpose transparency mat cardsFiled 1997·Granted Aug 8, 2000·20 cites·21 claims
- 0852US2018233566A1Field effect transistor structure with recessed interlayer dielectric and methodGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 0951US10026818B1Field effect transistor structure with recessed interlayer dielectric and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·0 cites·16 claims
- 1051US7101746B2Method to lower work function of gate electrode through Ge implantationCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Sep 5, 2006·3 cites·18 claims
- 1147US7999300B2Memory cell structure and method for fabrication thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2009·Granted Aug 16, 2011·0 cites·22 claims
- 1245US10347531B2Middle of the line (MOL) contact formation method and structureGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 1344US6872608B1Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarizationCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Mar 29, 2005·2 cites·15 claims
- 1441US7932178B2Integrated circuit having a plurality of MOSFET devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Apr 26, 2011·0 cites·6 claims
- 1539US4486042AGate latchCHEE JEFFREY·Filed 1982·Granted Dec 4, 1984·8 cites·10 claims
- 1637US2006205138A1Method to selectively form SiGe P type electrode and polysilicon N type electrode through planarizationCHARTERED SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1725USD519564SClip and coverCHEE JEFFREY JOCK FAI·Filed 2004·Granted Apr 25, 2006·1 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →