Inventor · disambiguated record
Christopher D. Sheraw
Also filed as: SHERAW CHRISTOPHER · SHERAW CHRISTOPHER D · SHERAW CHRISTOPHER DUNCAN
26 granted patents·3 pending applications·156 citations·filing 2004–2024
96Inventor score
Top patents by PatentIndex Score
29 records- 0193US10396078B2Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·9 cites·16 claims
- 0293US10020307B1Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 10, 2018·9 cites·11 claims
- 0392US9634084B1Conformal buffer layer in source and drain regions of fin-type transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 25, 2017·12 cites·19 claims
- 0491US8497212B2Filling narrow openings using ion beam etchBABICH KATHERINA E·Filed 2011·Granted Jul 30, 2013·15 cites·24 claims
- 0588US7485537B2Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thicknessIBM·Filed 2006·Granted Feb 3, 2009·12 cites·1 claims
- 0687US8940595B2Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levelsIBM·Filed 2013·Granted Jan 27, 2015·8 cites·20 claims
- 0786US7911024B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2010·Granted Mar 22, 2011·6 cites·4 claims
- 0885US7691716B2Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operationIBM·Filed 2008·Granted Apr 6, 2010·10 cites·5 claims
- 0983US9287399B2Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levelsIBM·Filed 2014·Granted Mar 15, 2016·5 cites·16 claims
- 1078US7375410B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2004·Granted May 20, 2008·17 cites·14 claims
- 1176US7115965B2Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operationIBM·Filed 2004·Granted Oct 3, 2006·16 cites·14 claims
- 1275US7956417B2Method of reducing stacking faults through annealingIBM·Filed 2010·Granted Jun 7, 2011·3 cites·6 claims
- 1375US7763518B2Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereofIBM·Filed 2008·Granted Jul 27, 2010·4 cites·17 claims
- 1475US7494918B2Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereofIBM·Filed 2006·Granted Feb 24, 2009·6 cites·7 claims
- 1574US8557649B2Method for controlling structure heightVENIGALLA RAJASEKHAR·Filed 2011·Granted Oct 15, 2013·4 cites·5 claims
- 1671US7498256B2Copper contact via structure using hybrid barrier layerIBM·Filed 2006·Granted Mar 3, 2009·5 cites·1 claims
- 1771US7491598B2CMOS circuits including a passive element having a low end resistanceIBM·Filed 2007·Granted Feb 17, 2009·3 cites·10 claims
- 1871US7227204B2Structure for improved diode idealityIBM·Filed 2005·Granted Jun 5, 2007·6 cites·4 claims
- 1968US7871893B2Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devicesIBM·Filed 2008·Granted Jan 18, 2011·4 cites·13 claims
- 2068US7674720B2Stacking fault reduction in epitaxially grown siliconIBM·Filed 2008·Granted Mar 9, 2010·2 cites·15 claims
- 2158US2025275204A1Gate-all-around field effect transistor with variable channel geometriesIBM·Filed 2024·Application pending·0 cites
- 2252US7893493B2Stacking fault reduction in epitaxially grown siliconIBM·Filed 2006·Granted Feb 22, 2011·0 cites·7 claims
- 2352US2008132025A1Ultra-thin soi vertical bipolar transistors with an inversion collector on thin-buried oxide (box) for low substrate-bias operation and methods thereofIBM·Filed 2007·Application pending·0 cites
- 2449US7820501B2Decoder for a stationary switch machineIBM·Filed 2006·Granted Oct 26, 2010·0 cites·11 claims
- 2548US7361959B2CMOS circuits including a passive element having a low end resistanceIBM·Filed 2005·Granted Apr 22, 2008·0 cites·10 claims
- 2646US10991689B2Additional spacer for self-aligned contact for only high voltage FinFETsGLOBALFOUNDRIES US INC·Filed 2019·Granted Apr 27, 2021·0 cites·20 claims
- 2746US2009090974A1Dual stress liner structure having substantially planar interface between liners and related methodIBM·Filed 2007·Application pending·0 cites
- 2844US10566328B2Integrated circuit products with gate structures positioned above elevated isolation structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·0 cites·17 claims
- 2937US9953873B2Methods of modulating the morphology of epitaxial semiconductor materialGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 24, 2018·0 cites·5 claims
Join the waitlist — get patent alerts
Get an alert when Christopher D. Sheraw files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →