Inventor · disambiguated record
Jay William Strane
Also filed as: STRANE JAY · STRANE JAY W · STRANE JAY WILLIAM
41 granted patents·29 pending applications·261 citations·filing 2002–2024
97Inventor score
Top patents by PatentIndex Score
70 records- 0195US8421077B2Replacement gate MOSFET with self-aligned diffusion contactJAIN SAMEER H·Filed 2010·Granted Apr 16, 2013·35 cites·20 claims
- 0293US8188574B2Pedestal guard ring having continuous M1 metal barrier connected to crack stopANGYAL MATTHEW S·Filed 2010·Granted May 29, 2012·21 cites·22 claims
- 0392US7041571B2Air gap interconnect structure and method of manufactureIBM·Filed 2004·Granted May 9, 2006·73 cites·16 claims
- 0491US9666474B2Uniform dielectric recess depth during fin revealIBM·Filed 2015·Granted May 30, 2017·5 cites·7 claims
- 0588US8685809B2Semiconductor structures having improved contact resistanceDORIS BRUCE B·Filed 2012·Granted Apr 1, 2014·7 cites·20 claims
- 0687US8299455B2Semiconductor structures having improved contact resistanceDORIS BRUCE B·Filed 2007·Granted Oct 30, 2012·10 cites·7 claims
- 0786US8101518B2Method and process for forming a self-aligned silicide contactCABRAL JR CYRIL·Filed 2008·Granted Jan 24, 2012·12 cites·27 claims
- 0880US11239119B2Replacement bottom spacer for vertical transport field effect transistorsIBM·Filed 2019·Granted Feb 1, 2022·2 cites·20 claims
- 0979US8039382B2Method for forming self-aligned metal silicide contactsIBM·Filed 2009·Granted Oct 18, 2011·6 cites·10 claims
- 1078US10636709B2Semiconductor fins with dielectric isolation at fin bottomIBM·Filed 2018·Granted Apr 28, 2020·1 cites·16 claims
- 1177US9984935B2Uniform dielectric recess depth during fin revealIBM·Filed 2017·Granted May 29, 2018·1 cites·10 claims
- 1277US7618891B2Method for forming self-aligned metal silicide contactsIBM·Filed 2006·Granted Nov 17, 2009·6 cites·22 claims
- 1373US10535550B2Protection of low temperature isolation fillIBM·Filed 2017·Granted Jan 14, 2020·1 cites·10 claims
- 1473US6989317B1Trench formation in semiconductor integrated circuits (ICs)IBM·Filed 2004·Granted Jan 24, 2006·19 cites·20 claims
- 1572US7790553B2Methods for forming high performance gates and structures thereofIBM·Filed 2008·Granted Sep 7, 2010·5 cites·14 claims
- 1671US6887785B1Etching openings of different depths using a single mask layer method and structureIBM·Filed 2004·Granted May 3, 2005·17 cites·17 claims
- 1770US12310090B2CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistorIBM·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 1870US7544610B2Method and process for forming a self-aligned silicide contactIBM·Filed 2004·Granted Jun 9, 2009·14 cites·34 claims
- 1968US11973125B2Self-aligned uniform bottom spacers for VTFETSIBM·Filed 2022·Granted Apr 30, 2024·0 cites·17 claims
- 2068US6809027B2Self-aligned borderless contactsIBM·Filed 2002·Granted Oct 26, 2004·12 cites·6 claims
- 2166US11646373B2Vertical field effect transistor with bottom spacerIBM·Filed 2021·Granted May 9, 2023·0 cites·20 claims
- 2266US11043429B2Semiconductor fins with dielectric isolation at fin bottomIBM·Filed 2020·Granted Jun 22, 2021·0 cites·19 claims
- 2365US12446290B2Asymmetric gate extension in stacked FETIBM·Filed 2023·Granted Oct 14, 2025·0 cites·20 claims
- 2465US10770361B2Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removalIBM·Filed 2020·Granted Sep 8, 2020·0 cites·20 claims
- 2564US6806177B2Method of making self-aligned borderless contactsIBM·Filed 2003·Granted Oct 19, 2004·10 cites·14 claims
- 2662US11251287B2Self-aligned uniform bottom spacers for VTFETSIBM·Filed 2020·Granted Feb 15, 2022·0 cites·18 claims
- 2761US12268030B2Self-aligned C-shaped vertical field effect transistorIBM·Filed 2021·Granted Apr 1, 2025·0 cites·20 claims
- 2861US11615990B2CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistorIBM·Filed 2020·Granted Mar 28, 2023·0 cites·20 claims
- 2961US10892193B2Controlling active fin height of FinFET deviceIBM·Filed 2019·Granted Jan 12, 2021·0 cites·16 claims
- 3061US2025380452A1Shaped epitaxyIBM·Filed 2024·Application pending·0 cites
- 3160US12183740B2Stacked field-effect transistorsIBM·Filed 2022·Granted Dec 31, 2024·0 cites·20 claims
- 3260US11217692B2Vertical field effect transistor with bottom spacerIBM·Filed 2020·Granted Jan 4, 2022·0 cites·20 claims
- 3360US9941134B2Uniform dielectric recess depth during fin revealIBM·Filed 2017·Granted Apr 10, 2018·0 cites·16 claims
- 3460US2025167118A1Stacked field-effect transistor device with backside cut for top source/drain accessIBM·Filed 2023·Application pending·0 cites
- 3560US2025359322A1Dielectric inner spacers for nanosheet transistorsIBM·Filed 2024·Application pending·0 cites
- 3659US12356711B2Late gate extensionIBM·Filed 2021·Granted Jul 8, 2025·0 cites·18 claims
- 3759US11189532B2Dual width finned semiconductor structureIBM·Filed 2019·Granted Nov 30, 2021·0 cites·19 claims
- 3859US9984916B2Uniform dielectric recess depth during fin revealIBM·Filed 2017·Granted May 29, 2018·0 cites·7 claims
- 3959US2025239521A1Stacked field effect transistor with epitaxy cut for source/drain contactIBM·Filed 2024·Application pending·0 cites
- 4059US2025248114A1Stacked transistor frontside contact formationIBM·Filed 2024·Application pending·0 cites
- 4159US2025203946A1Semiconductor device with stacked device typesIBM·Filed 2023·Application pending·0 cites
- 4259US2025159997A1Enlarged bottom contact area in stacked transistorsIBM·Filed 2023·Application pending·0 cites
- 4359US2025063795A1Local trapped metal contact for stacked fetIBM·Filed 2023·Application pending·0 cites
- 4459US2025089336A1Dual sided circuit connectionsIBM·Filed 2023·Application pending·0 cites
- 4558US2024429098A1Merged self-aligned backside contactIBM·Filed 2023·Application pending·0 cites
- 4658US2025113560A1Field-effect transistor crescent-shaped dielectric isolationIBM·Filed 2023·Application pending·0 cites
- 4758US2025185298A1U-shaped spacer to protect the intra-device space region for stacked fetIBM·Filed 2023·Application pending·0 cites
- 4857US10665514B2Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removalIBM·Filed 2018·Granted May 26, 2020·0 cites·16 claims
- 4957US2024304519A1Frontside to backside signal via in edge cellIBM·Filed 2023·Application pending·0 cites
- 5057US2024371728A1Backside contacts for source/drain regionsIBM·Filed 2023·Application pending·0 cites
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →