Inventor · disambiguated record
Hsiu-Chun Lee
Also filed as: LEE HSIU-CHUN
5 granted patents·6 pending applications·11 citations·filing 2003–2016
71Inventor score
Top patents by PatentIndex Score
11 records- 0178US8252684B1Method of forming a trench by a silicon-containing maskLEE HSIU-CHUN·Filed 2011·Granted Aug 28, 2012·6 cites·7 claims
- 0259US7569451B2Method of fabricating an isolation shallow trenchNANYA TECHNOLOGY CORP·Filed 2008·Granted Aug 4, 2009·3 cites·19 claims
- 0347US9985105B2Method of manufacturing a PMOS transistor comprising a dual work function metal gateNANYA TECHNOLOGY CORP·Filed 2016·Granted May 29, 2018·0 cites·15 claims
- 0445US2014264640A1Semiconductor device and method for fabricating the sameNANYA TECHNOLOGY CORP·Filed 2013·Application pending·0 cites
- 0543US8377632B2Method of reducing microloading effectNANYA TECHNOLOGY CORP·Filed 2011·Granted Feb 19, 2013·0 cites·12 claims
- 0642US6974741B2Method for forming shallow trench in semiconductor deviceNANYA TECHNOLOGY CORPORATIION·Filed 2004·Granted Dec 13, 2005·2 cites·10 claims
- 0737US2005147926A1Method for processing photoresistNANYA TECHNOLOGY CORP·Filed 2004·Application pending·0 cites
- 0836US2005118531A1Method for controlling critical dimension by utilizing resist sidewall protectionFiled 2003·Application pending·0 cites
- 0933US2006154435A1Method of fabricating trench isolation for trench-capacitor dram devicesLEE HSIU-CHUN·Filed 2005·Application pending·0 cites
- 1032US2012305525A1Method of reducing striation on a sidewall of a recessLEE HSIU-CHUN·Filed 2011·Application pending·0 cites
- 1131US2012302030A1Method of fabricating a deep trench deviceLEE HSIU-CHUN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →