Semiconductor device and method for fabricating the same

Abstract

The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a U-shaped gate dielectric layer formed on the substrate; and   a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer comprises a first conductive type metal layer and a second conductive type metal layer.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the U-shaped gate dielectric layer comprises a horizontal portion and two vertical portions, and the two vertical portions are located at opposite ends of the horizontal portion. 
     
     
         3 . The semiconductor device as claimed in  claim 2 , wherein the dual work function metal gate layer comprises:
 two first conductive type metal layers adjacent to the vertical portions of the U-shaped gate dielectric layer; and   the second conductive type metal layer sandwiched between two first conductive type metal layers.   
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the first conductive type metal layer is a p +  metal layer and the second conductive type metal layer is an n +  metal layer. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the first conductive type metal layer is an n +  metal layer and the second conductive type metal layer is a p +  metal layer. 
     
     
         6 . The semiconductor device as claimed in  claim 1 , wherein the n +  metal layer has a work function of about 4.1-4.9. 
     
     
         7 . The semiconductor device as claimed in  claim 5 , wherein the n +  metal layer comprises scandium (Sc), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium, (Ti), tantalum (Ta) or niobium (Nb). 
     
     
         8 . The semiconductor device as claimed in  claim 5 , wherein the p +  metal layer has a work function of about 4.7-5.0. 
     
     
         9 . The semiconductor device as claimed in  claim 5 , wherein the p +  metal layer comprises tungsten (W), platinum (Pt), ruthenium (Ru), molybdenum (Mo), titanium carbide (TiC), zirconium arbide (ZrC), tantalum carbide (TaC), tungsten carbide (WC), titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO). 
     
     
         10 . The semiconductor device as claimed in  claim 1 , wherein the U-shaped gate dielectric layer comprises high-k dielectric material. 
     
     
         11 . The semiconductor device as claimed in  claim 10 , wherein the high-k dielectric material comprises HfO 2 , ZrO 2 , TiO 2 , Al 2 O 3 , HfSiO, HfSiON, HfTaO, HfSiO, HfZrO or combinations thereof. 
     
     
         12 . The semiconductor device as claimed in  claim 1 , further comprising:
 an inter-layer dielectric layer (ILD) formed on the substrate and on a sidewall of the dual work function metal gate layer.   
     
     
         13 . The semiconductor device as claimed in  claim 12 , further comprising:
 a spacer formed on the substrate, wherein the spacer is formed between the inter-layer dielectric layer (ILD) and the dual work function metal gate layer.   
     
     
         14 . A method for fabricating a semiconductor device, comprising:
 providing a substrate;   forming a dummy gate on the substrate;   forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate;   performing a first chemical mechanical polishing (CMP) process to the inter-layer dielectric layer (ILD) to expose an upper surface of the dummy gate;   forming a metal layer on the upper surface of the dummy gate;   removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD);   conformally forming a gate dielectric layer in the trench;   conformally forming a first conductive type metal layer on the gate dielectric layer;   removing the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD) and to expose a portion of the gate dielectric layer;   filling a second conductive type metal layer in the gap, wherein the second conductive type metal layer is sandwiched between two first conductive type metal layers to form a dual work function metal gate layer; and   performing a second chemical mechanical polishing (CMP) process to the second conductive type metal layer and the metal layer to expose an upper surface of the dual work function metal gate layer.   
     
     
         15 . The method for fabricating a semiconductor device as claimed in  claim 14 , before forming the inter-layer dielectric layer (ILD) on the dummy gate and the substrate, further comprising:
 forming a spacer on a sidewall of the dummy gate.   
     
     
         16 . The method for fabricating a semiconductor device as claimed in  claim 14 , wherein the metal layer comprises p +  metal layer or n +  metal layer. 
     
     
         17 . The method for fabricating a semiconductor device as claimed in  claim 14 , after removing the first conductive type metal layer and the gate dielectric layer over the metal layer, wherein the gate dielectric layer has a U-shaped structure, and the U-shaped gate dielectric layer comprises a horizontal portion and two vertical portions, and the two vertical portions are located at opposite ends of the horizontal portion. 
     
     
         18 . The method for fabricating a semiconductor device as claimed in  claim 17 , wherein two first conductive type metal layers are adjacent to the vertical portions of the U-shaped gate dielectric layer. 
     
     
         19 . The method for fabricating a semiconductor device as claimed in  claim 14 , wherein the gate dielectric layer comprises high-k dielectric material. 
     
     
         20 . The method for fabricating a semiconductor device as claimed in  claim 14 , wherein the first conductive type metal layer is a p +  metal layer and the second conductive type metal layer is an n +  metal layer. 
     
     
         21 . The method for fabricating a semiconductor device as claimed in  claim 14 , wherein the first conductive type metal layer is an n +  metal layer and the second conductive type metal layer is a p +  metal layer. 
     
     
         22 . The method for fabricating a semiconductor device as claimed in  claim 14 , wherein a width of the trench is larger than that of the gap.