Inventor · disambiguated record
Michael A. Guillorn
Also filed as: GUILLORN MICHAEL · GUILLORN MICHAEL A
234 granted patents·33 pending applications·2,822 citations·filing 2001–2022
99Inventor score
Top patents by PatentIndex Score
267 records- 0199US10074575B1Integrating and isolating nFET and pFET nanosheet transistors on a substrateIBM·Filed 2017·Granted Sep 11, 2018·45 cites·19 claims
- 0299US9997519B1Dual channel structures with multiple threshold voltagesIBM·Filed 2017·Granted Jun 12, 2018·102 cites·20 claims
- 0399US9755017B1Co-integration of silicon and silicon-germanium channels for nanosheet devicesIBM·Filed 2016·Granted Sep 5, 2017·48 cites·18 claims
- 0499US9647139B2Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacerIBM·Filed 2015·Granted May 9, 2017·34 cites·14 claims
- 0599US9362355B1Nanosheet MOSFET with full-height air-gap spacerIBM·Filed 2015·Granted Jun 7, 2016·198 cites·6 claims
- 0699US8927968B2Accurate control of distance between suspended semiconductor nanowires and substrate surfaceIBM·Filed 2013·Granted Jan 6, 2015·87 cites·14 claims
- 0799US8637359B2Fin-last replacement metal gate FinFET processCHANG JOSEPHINE B·Filed 2011·Granted Jan 28, 2014·71 cites·17 claims
- 0899US7923337B2Fin field effect transistor devices with self-aligned source and drain regionsIBM·Filed 2007·Granted Apr 12, 2011·234 cites·19 claims
- 0999US7892945B2Nanowire mesh device and method of fabricating sameIBM·Filed 2010·Granted Feb 22, 2011·97 cites·13 claims
- 1098US9871140B1Dual strained nanosheet CMOS and methods for fabricatingIBM·Filed 2017·Granted Jan 16, 2018·37 cites·19 claims
- 1198US9748404B1Method for fabricating a semiconductor device including gate-to-bulk substrate isolationIBM·Filed 2016·Granted Aug 29, 2017·32 cites·18 claims
- 1298US9728542B1High density programmable e-fuse co-integrated with vertical FETsIBM·Filed 2016·Granted Aug 8, 2017·37 cites·16 claims
- 1398US9576817B1Pattern decomposition for directed self assembly patterns templated by sidewall image transferIBM·Filed 2015·Granted Feb 21, 2017·40 cites·17 claims
- 1498US8492208B1Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate processCOHEN GUY·Filed 2012·Granted Jul 23, 2013·35 cites·19 claims
- 1598US8440523B1Micromechanical device and methods to fabricate same using hard mask resistant to structure release etchGUILLORN MICHAEL A·Filed 2011·Granted May 14, 2013·143 cites·16 claims
- 1698US7408186B2Controlled alignment catalytically grown nanostructuresUT BATTELLE LLC·Filed 2005·Granted Aug 5, 2008·92 cites·2 claims
- 1797US10621302B2Classification and localization of hotspots in integrated physical design layoutsIBM·Filed 2018·Granted Apr 14, 2020·9 cites·17 claims
- 1897US10170584B2Nanosheet field effect transistors with partial inside spacersIBM·Filed 2017·Granted Jan 1, 2019·11 cites·14 claims
- 1997US9911592B2Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structureIBM·Filed 2016·Granted Mar 6, 2018·13 cites·19 claims
- 2097US9853132B2Nanosheet MOSFET with full-height air-gap spacerIBM·Filed 2016·Granted Dec 26, 2017·17 cites·18 claims
- 2197US9831324B1Self-aligned inner-spacer replacement process using implantationIBM·Filed 2016·Granted Nov 28, 2017·14 cites·11 claims
- 2297US9721888B2Trench silicide with self-aligned contact viasIBM·Filed 2015·Granted Aug 1, 2017·21 cites·15 claims
- 2397US9653547B1Integrated etch stop for capped gate and method for manufacturing the sameIBM·Filed 2016·Granted May 16, 2017·22 cites·17 claims
- 2497US9646883B2Chemoepitaxy etch trim using a self aligned hard mask for metal line to viaIBM·Filed 2015·Granted May 9, 2017·10 cites·16 claims
- 2597US9508829B1Nanosheet MOSFET with full-height air-gap spacerIBM·Filed 2016·Granted Nov 29, 2016·22 cites·14 claims
- 2697US9306164B1Electrode pair fabrication using directed self assembly of diblock copolymersIBM·Filed 2015·Granted Apr 5, 2016·22 cites·8 claims
- 2797US8656322B1Fin design level mask decomposition for directed self assemblyIBM·Filed 2013·Granted Feb 18, 2014·27 cites·20 claims
- 2897US8395220B2Nanomesh SRAM cellCHANG JOSEPHINE·Filed 2012·Granted Mar 12, 2013·33 cites·19 claims
- 2997US8084308B2Single gate inverter nanowire meshCHANG JOSEPHINE·Filed 2009·Granted Dec 27, 2011·83 cites·9 claims
- 3097US7893492B2Nanowire mesh device and method of fabricating sameIBM·Filed 2009·Granted Feb 22, 2011·76 cites·10 claims
- 3196US10096607B1Three-dimensional stacked junctionless channels for dense SRAMIBM·Filed 2017·Granted Oct 9, 2018·14 cites·20 claims
- 3296US8216902B2Nanomesh SRAM cellCHANG JOSEPHINE·Filed 2009·Granted Jul 10, 2012·50 cites·5 claims
- 3395US9812321B2Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structureIBM·Filed 2016·Granted Nov 7, 2017·8 cites·20 claims
- 3495US9437443B2Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitridesGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 6, 2016·26 cites·19 claims
- 3595US9029834B2Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectricBANGSARUNTIP SARUNYA·Filed 2010·Granted May 12, 2015·22 cites·20 claims
- 3695US8969965B2Fin-last replacement metal gate FinFETIBM·Filed 2014·Granted Mar 3, 2015·18 cites·6 claims
- 3795US8816328B2Patterning contacts in carbon nanotube devicesCHANG JOSEPHINE B·Filed 2012·Granted Aug 26, 2014·13 cites·14 claims
- 3895US8586449B1Raised isolation structure self-aligned to fin structuresCHANG JOSEPHINE B·Filed 2012·Granted Nov 19, 2013·23 cites·22 claims
- 3995US8422273B2Nanowire mesh FET with multiple threshold voltagesCHANG JOSEPHINE·Filed 2009·Granted Apr 16, 2013·39 cites·9 claims
- 4094US10242920B2Integrating and isolating NFET and PFET nanosheet transistors on a substrateIBM·Filed 2018·Granted Mar 26, 2019·7 cites·20 claims
- 4194US10037885B2Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacerIBM·Filed 2017·Granted Jul 31, 2018·6 cites·20 claims
- 4294US9559284B2Silicided nanowires for nanobridge weak linksGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 31, 2017·8 cites·12 claims
- 4394US9536794B2Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growthIBM·Filed 2015·Granted Jan 3, 2017·10 cites·20 claims
- 4494US9391163B2Stacked planar double-gate lamellar field-effect transistorIBM·Filed 2014·Granted Jul 12, 2016·11 cites·1 claims
- 4594US9362354B1Tuning gate lengths in semiconductor device structuresIBM·Filed 2015·Granted Jun 7, 2016·10 cites·15 claims
- 4694US8803129B2Patterning contacts in carbon nanotube devicesCHANG JOSEPHINE B·Filed 2011·Granted Aug 12, 2014·12 cites·16 claims
- 4794US8716695B2Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate processIBM·Filed 2013·Granted May 6, 2014·16 cites·11 claims
- 4894US8642403B1Replacement contacts for all-around contactsCOHEN GUY M·Filed 2012·Granted Feb 4, 2014·16 cites·20 claims
- 4994US8536018B1Maskless inter-well deep trench isolation structure and methods of manufactureANDERSON BRENT A·Filed 2012·Granted Sep 17, 2013·19 cites·19 claims
- 5094US8470628B2Methods to fabricate silicide micromechanical deviceGUILLORN MICHAEL A·Filed 2011·Granted Jun 25, 2013·11 cites·16 claims
Showing the top 50 of 267 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →