Inventor · disambiguated record
Kenneth J. Reyer
Also filed as: REYER KENNETH J
16 granted patents·3 pending applications·87 citations·filing 2003–2019
92Inventor score
Top patents by PatentIndex Score
19 records- 0191US7064990B1Method and apparatus for implementing multiple column redundancy for memoryIBM·Filed 2005·Granted Jun 20, 2006·29 cites·17 claims
- 0283US7471590B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2007·Granted Dec 30, 2008·11 cites·5 claims
- 0382US10943647B1Bit-line mux driver with diode header for computer memoryIBM·Filed 2019·Granted Mar 9, 2021·5 cites·20 claims
- 0478US7176725B2Fast pulse powered NOR decode apparatus for semiconductor devicesIBM·Filed 2005·Granted Feb 13, 2007·9 cites·19 claims
- 0576US7283417B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2005·Granted Oct 16, 2007·8 cites·14 claims
- 0673US10930339B1Voltage bitline high (VBLH) regulation for computer memoryIBM·Filed 2019·Granted Feb 23, 2021·3 cites·20 claims
- 0770US7099206B2High density bitline selection apparatus for semiconductor memory devicesIBM·Filed 2005·Granted Aug 29, 2006·7 cites·21 claims
- 0866US9224437B2Gated-feedback sense amplifier for single-ended local bit-line memoriesGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 29, 2015·3 cites·20 claims
- 0963US9025403B1Dynamic cascode-managed high-voltage word-line driver circuitIBM·Filed 2013·Granted May 5, 2015·2 cites·13 claims
- 1058US7068554B1Apparatus and method for implementing multiple memory redundancy with delay tracking clockIBM·Filed 2005·Granted Jun 27, 2006·4 cites·17 claims
- 1156US7688650B2Write control method for a memory array configured with multiple memory subarraysIBM·Filed 2008·Granted Mar 30, 2010·2 cites·5 claims
- 1253US7299374B2Clock control method and apparatus for a memory arrayIBM·Filed 2005·Granted Nov 20, 2007·2 cites·20 claims
- 1351US2008028255A1Clock control method and apparatus for a memory arrayIBM·Filed 2007·Application pending·0 cites
- 1450US7170320B2Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steeringIBM·Filed 2005·Granted Jan 30, 2007·1 cites·19 claims
- 1547US9748958B2Dynamic high voltage driver with adjustable clamped output levelIBM·Filed 2016·Granted Aug 29, 2017·0 cites·20 claims
- 1647US7380191B2ABIST data compression and serialization for memory built-in self test of SRAM with redundancyIBM·Filed 2005·Granted May 27, 2008·1 cites·6 claims
- 1745US9053770B1Dynamic cascode-managed high-voltage word-line driver circuitIBM·Filed 2014·Granted Jun 9, 2015·0 cites·7 claims
- 1835US2005127441A1Body contact layout for semiconductor-on-insulator devicesIBM·Filed 2003·Application pending·0 cites
- 1934US2006181950A1Apparatus and method for SRAM decoding with single signal synchronizationIBM·Filed 2005·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →