Body contact layout for semiconductor-on-insulator devices

Abstract

A method and structure is provided for an improved body contact layout for semiconductor-on-insulator (SOI) devices. In one embodiment, an insulated gate field effect transistor and method for fabrication of such a transistor is provided. The insulated gate field effect transistor includes a source, a drain, and a channel formed in a layer of a single-crystal semiconductor. The layer is disposed over and insulated from a bulk semiconductor layer of a substrate by a buried insulator layer. A gate conductor is disposed in an annular pattern overlying the channel, such that the gate conductor surrounds one of the source and drain disposed to the inside of the annular pattern, the other of the source and drain being disposed to the outside of the annular pattern. A second conductive pattern is connected to the annular pattern of the gate conductor. A conductive body contact is also disposed in the vicinity of the second conductive pattern.

1 . An insulated gate field effect transistor, comprising: 
 a source, a drain, and channel formed in a layer of a single-crystal semiconductor;    said layer disposed over and insulated from a bulk semiconductor layer of a substrate by a buried insulator layer;    a gate conductor disposed in an annular pattern overlying said channel, such that said gate conductor surrounds one of said source and said drain disposed to the inside of said annular pattern, the other of said source and said drain being disposed to the outside of said annular pattern, said gate conductor further including a second pattern connected to said annular pattern; and    a conductive body contact to said single-crystal semiconductor layer disposed in the vicinity of said second pattern.    
   
   
       2 . The insulated gate field effect transistor of  claim 1 , wherein said source, drain and channel region are disposed in an active area of said layer bounded by one or more isolation structures.  
   
   
       3 . The insulated gate field effect transistor of  claim 1 , wherein said second pattern extends linearly between said annular pattern and an edge of said active area.  
   
   
       4 . The insulated gate field effect transistor of  claim 1 , wherein said annular pattern includes a pair of parallel portions oriented in a first direction substantially parallel to an edge of said active area and further includes angled portions oriented at an angle to said first direction.  
   
   
       5 . The insulated gate field effect transistor of  claim 4 , wherein at least some of said angled portions are oriented at angles between about 30 degrees and 60 degrees with respect to said first direction.  
   
   
       6 . The insulated gate field effect transistor of  claim 4 , wherein at least some of said angled portions are oriented at angles of about 45 degrees.  
   
   
       7 . The insulated gate field effect transistor of  claim 1 , wherein said transistor is an n-type FET, the source is disposed to the outside of the annular pattern, and the body contact is disposed on a region of said layer adjacent to said source.  
   
   
       8 . The insulated gate field effect transistor of  claim 1 , wherein said gate conductor further includes a third pattern connected to said annular pattern, said second and third patterns extending from first and second locations of said annular pattern in substantially opposite directions.  
   
   
       9 . The insulated gate field effect transistor of  claim 8 , wherein said second and said third patterns extend linearly between said annular pattern and edges of said active area.  
   
   
       10 . An insulated gate field effect transistor, comprising: 
 a source, a drain, and channel formed in a layer of a single-crystal semiconductor,    said layer disposed over and insulated from a bulk semiconductor substrate by a buried insulator layer;    a gate conductor including a first multiple finger pattern overlying said channel and a second multiple finger pattern overlying said channel, and a connecting pattern conductively connecting said first and second multiple finger patterns; and    an electrically conductive body contact to said single-crystal semiconductor layer disposed in the vicinity of said connecting pattern.    
   
   
       11 . The insulated gate field effect transistor of  claim 10 , wherein said first and said second multiple finger patterns each have two fingers, wherein one of said source and said drain is disposed between said two fingers, and the other of said source and said drain is disposed to the outside of said two fingers.  
   
   
       12 . The insulated gate field effect transistor of  claim 10  wherein said gate conductor includes four fingers.  
   
   
       13 . The insulated gate field effect transistor of  claim 10  wherein said gate conductor includes a multiple n of two fingers, wherein n is greater than two.  
   
   
       14 . The insulated gate field effect transistor of  claim 10 , wherein said source, drain and channel region are disposed in an active area of said layer bounded by one or more isolation structures.  
   
   
       15 . The insulated gate field effect transistor of  claim 10 , wherein said transistor is an n-type FET, and said source is disposed to the outside of the annular pattern, and the body contact is disposed on a region of said layer adjacent to said source.  
   
   
       16 . A method of making an insulated gate field effect transistor, comprising: 
 providing a substrate having a single-crystal semiconductor layer separated from a bulk semiconductor portion by a buried insulator layer;    forming a source, a drain, and a channel in said single-crystal semiconductor layer;    forming a gate conductor disposed in an annular pattern overlying said channel, such that said gate conductor surrounds one of said source and said drain disposed to the inside of said annular pattern, the other of said source and said drain being disposed to the outside of said annular pattern, said gate conductor further including a second pattern connected to said annular pattern; and    forming an electrically conductive contact to said single-crystal semiconductor layer in the vicinity of said second pattern.    
   
   
       17 . The method of  claim 16  wherein said gate conductor is patterned to form said annular pattern and said second pattern prior to depositing at least one material selected from the group consisting of heavily doped polysilicon, metals and metal compounds to form said electrically conductive contact.  
   
   
       18 . The method of  claim 17  wherein said material is deposited prior to implanting ions to form said source, and said drain, said channel remaining as an area disposed under at least portions of said gate conductor between said source and said drain.  
   
   
       19 . The method of  claim 15 , further comprising: 
 patterning an active area in said single-crystal semiconductor layer;    providing trench isolations to isolate said active area,    wherein said source, said drain, and said channel are formed in said active area.    
   
   
       20 . The method of  claim 15 , wherein said second pattern extends linearly between said annular pattern and an edge of said active area.