Inventor · disambiguated record
Thomas S. Kanarsky
Also filed as: KANARSKY THOMAS · KANARSKY THOMAS S · KANARSKY THOMAS SAFRON
31 granted patents·6 pending applications·1,047 citations·filing 1995–2011
98Inventor score
Top patents by PatentIndex Score
37 records- 0198US7250658B2Hybrid planar and FinFET CMOS devicesIBM·Filed 2005·Granted Jul 31, 2007·164 cites·6 claims
- 0297US8043920B2finFETS and methods of making sameIBM·Filed 2009·Granted Oct 25, 2011·91 cites·12 claims
- 0397US7041538B2Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2003·Granted May 9, 2006·124 cites·11 claims
- 0495US7989298B1Transistor having V-shaped embedded stressorIBM·Filed 2010·Granted Aug 2, 2011·27 cites·20 claims
- 0595US6911383B2Hybrid planar and finFET CMOS devicesIBM·Filed 2003·Granted Jun 28, 2005·109 cites·11 claims
- 0694US6846734B2Method and process to make multiple-threshold metal gates CMOS technologyIBM·Filed 2002·Granted Jan 25, 2005·105 cites·27 claims
- 0792US7968915B2Dual stress memorization technique for CMOS applicationIBM·Filed 2009·Granted Jun 28, 2011·17 cites·6 claims
- 0890US7834399B2Dual stress memorization technique for CMOS applicationIBM·Filed 2007·Granted Nov 16, 2010·15 cites·6 claims
- 0990US7314789B2Structure and method to generate local mechanical gate stress for MOSFET channel mobility modificationIBM·Filed 2006·Granted Jan 1, 2008·13 cites·16 claims
- 1089US8410544B2finFETs and methods of making sameCHAN KEVIN K·Filed 2011·Granted Apr 2, 2013·10 cites·20 claims
- 1189US6677646B2Method and structure of a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2002·Granted Jan 13, 2004·41 cites·9 claims
- 1286US6914303B2Ultra thin channel MOSFETIBM·Filed 2003·Granted Jul 5, 2005·33 cites·4 claims
- 1381US7173312B2Structure and method to generate local mechanical gate stress for MOSFET channel mobility modificationIBM·Filed 2004·Granted Feb 6, 2007·20 cites·11 claims
- 1481US5536388AVertical electroetch tool nozzle and methodIBM·Filed 1995·Granted Jul 16, 1996·42 cites·13 claims
- 1580US7413941B2Method of fabricating sectional field effect devicesIBM·Filed 2006·Granted Aug 19, 2008·5 cites·1 claims
- 1680US7018891B2Ultra-thin Si channel CMOS with improved series resistanceIBM·Filed 2003·Granted Mar 28, 2006·26 cites·8 claims
- 1779US6218236B1Method of forming a buried bitline in a vertical DRAM deviceIBM·Filed 1999·Granted Apr 17, 2001·36 cites·14 claims
- 1874US7659153B2Sectional field effect devices and method of fabricationIBM·Filed 2008·Granted Feb 9, 2010·3 cites·14 claims
- 1973US6583462B1Vertical DRAM having metallic node conductorIBM·Filed 2000·Granted Jun 24, 2003·14 cites·11 claims
- 2069US6905941B2Structure and method to fabricate ultra-thin Si channel devicesIBM·Filed 2003·Granted Jun 14, 2005·13 cites·14 claims
- 2168US7871893B2Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devicesIBM·Filed 2008·Granted Jan 18, 2011·4 cites·13 claims
- 2267US5796168AMetallic interconnect pad, and integrated circuit structure using same, with reduced undercutIBM·Filed 1996·Granted Aug 18, 1998·30 cites·8 claims
- 2365US6333533B1Trench storage DRAM cell with vertical three-sided transfer deviceIBM·Filed 1999·Granted Dec 25, 2001·20 cites·20 claims
- 2463US7211490B2Ultra thin channel MOSFETIBM·Filed 2005·Granted May 1, 2007·2 cites·15 claims
- 2563US6258661B1Formation of out-diffused bitline by laser annealIBM·Filed 2000·Granted Jul 10, 2001·7 cites·12 claims
- 2657US7388258B2Sectional field effect devicesIBM·Filed 2003·Granted Jun 17, 2008·4 cites·12 claims
- 2757US5759437AEtching of Ti-W for C4 reworkIBM·Filed 1996·Granted Jun 2, 1998·20 cites·17 claims
- 2854US6207493B1Formation of out-diffused bitline by laser annealIBM·Filed 1998·Granted Mar 27, 2001·16 cites·21 claims
- 2954US5620611AMethod to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder padsIBM·Filed 1996·Granted Apr 15, 1997·16 cites·8 claims
- 3051US6238589B1Methods for monitoring components in the TiW etching bath used in the fabrication of C4sIBM·Filed 1998·Granted May 29, 2001·14 cites·24 claims
- 3144US6376873B1Vertical DRAM cell with robust gate-to-storage node isolationIBM·Filed 1999·Granted Apr 23, 2002·6 cites·7 claims
- 3243US2008083955A1Intrinsically stressed liner and fabrication methods thereofKANARSKY THOMAS S·Filed 2006·Application pending·0 cites
- 3342US2009242989A1Complementary metal-oxide-semiconductor device with embedded stressorCHAN KEVIN K·Filed 2008·Application pending·0 cites
- 3442US2005003589A1Structure and method to fabricate ultra-thin Si channel devicesIBM·Filed 2004·Application pending·0 cites
- 3538US2005106788A1Method and process to make multiple-threshold metal gates CMOS technologyIBM·Filed 2004·Application pending·0 cites
- 3636US2001018247A1Process of manufacturing a dynamic random access memory deviceFiled 2001·Application pending·0 cites
- 3735US2001017384A1Method of forming a buried bitline in a vertical DRAM deviceIBM·Filed 2001·Application pending·0 cites
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