Structure and method to fabricate ultra-thin Si channel devices

Abstract

A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

1 - 11 . (Cancelled)  
   
   
       12 . A semiconductor structure comprising 
 a silicon-on-insulator (SOI) comprising at least a top Si-containing layer located on a buried insulating layer; and    an oxide filled trench isolation region located in said top Si-containing layer and a portion of said buried insulating layer, wherein no undercut regions are located beneath the top Si-containing layer.    
   
   
       13 . The semiconductor structure of  claim 12  wherein said top Si-containing layer has a vertical thickness of less than about 20 nm.  
   
   
       14 . The semiconductor structure of  claim 12  wherein said oxide filled trench isolation region comprises a deposited oxide.  
   
   
       15 . The semiconductor structure of  claim 12  wherein a portion of said top Si-containing layer serves as a channel region of a transistor.  
   
   
       16 . The semiconductor structure of  claim 12  further comprising a transistor located atop the top Si-containing layer.  
   
   
       17 . The semiconductor structure of  claim 12  wherein the oxide filled trench isolation region has a height that is above the upper surface of the top Si-containing layer.  
   
   
       18 . The semiconductor structure of  claim 17  wherein said oxide filled trench isolation region slopes downward towards said upper surface of the top Si-containing layer.  
   
   
       19 . The semiconductor structure of  claim 12  wherein the oxide filled trench isolation region has a height that is below the upper surface of the top Si-containing layer.  
   
   
       20 . The semiconductor structure of  claim 19  wherein said oxide filled trench isolation region slopes upward towards said upper surface of the top Si-containing layer.