Inventor · disambiguated record
Craig Child
Also filed as: CHILD CRAIG · CHILD CRAIG M · CHILD CRAIG MICHAEL · CHILD JR CRAIG MICHAEL
16 granted patents·3 pending applications·54 citations·filing 2009–2024
90Inventor score
Top patents by PatentIndex Score
19 records- 0194US9786545B1Method of forming ANA regions in an integrated circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 10, 2017·11 cites·20 claims
- 0292US9431294B2Methods of producing integrated circuits with an air gapGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 30, 2016·14 cites·19 claims
- 0389US9818623B2Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 14, 2017·6 cites·17 claims
- 0484US9691971B2Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 27, 2017·5 cites·18 claims
- 0580US7932613B2Interconnect structure for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2009·Granted Apr 26, 2011·8 cites·13 claims
- 0675US10181420B2Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 15, 2019·2 cites·10 claims
- 0772US9812396B1Interconnect structure for semiconductor devices with multiple power rails and redundancyGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·2 cites·8 claims
- 0871US10566231B2Interconnect formation with chamferless via, and related interconnectGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·2 cites·14 claims
- 0971US8822342B2Method to reduce depth delta between dense and wide features in dual damascene structuresSRIVASTAVA RAVI PRAKASH·Filed 2010·Granted Sep 2, 2014·3 cites·18 claims
- 1067US12453102B2Vertical memory devicesGLOBALFOUNDRIES US INC·Filed 2022·Granted Oct 21, 2025·0 cites·9 claims
- 1160US2025349647A1Thermal Resistance Extraction for Semiconductor DevicesIBM·Filed 2024·Application pending·0 cites
- 1257US11367750B2Vertical memory devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 21, 2022·0 cites·18 claims
- 1355US8513109B2Method of manufacturing an interconnect structure for a semiconductor deviceCHILD CRAIG·Filed 2011·Granted Aug 20, 2013·1 cites·16 claims
- 1447US10643891B2Via structures and via patterning using oblique angle deposition processesGLOBALFOUNDRIES INC·Filed 2018·Granted May 5, 2020·0 cites·20 claims
- 1546US2021305152A1Inverted, self-aligned top-via structuresIBM·Filed 2020·Application pending·0 cites
- 1644US9165770B2Methods for fabricating integrated circuits using improved masksGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 20, 2015·0 cites·14 claims
- 1743US11417525B2Multiple patterning with mandrel cuts defined by block masksGLOBALFOUNDRIES US INC·Filed 2018·Granted Aug 16, 2022·0 cites·8 claims
- 1831US10340177B2Devices and methods of reducing damage during BEOL M1 integrationGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 2, 2019·0 cites·10 claims
- 1927US2016372413A1Unique bi-layer etch stop to protect conductive structures during a metal hard mask removal process and methods of using sameGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →