Inventor · disambiguated record
Jarvis Benjamin Jacobs
Also filed as: JACOBS JARVIS · JACOBS JARVIS B · JACOBS JARVIS BENJAMIN
21 granted patents·8 pending applications·176 citations·filing 1997–2024
94Inventor score
Top patents by PatentIndex Score
29 records- 0186US9431286B1Deep trench with self-aligned sinkerTEXAS INSTRUMENTS INC·Filed 2014·Granted Aug 30, 2016·8 cites·7 claims
- 0286US5936278ASemiconductor on silicon (SOI) transistor with a halo implantTEXAS INSTRUMENTS INC·Filed 1997·Granted Aug 10, 1999·75 cites·6 claims
- 0385US6866974B2Semiconductor process using delay-compensated exposureTEXAS INSTRUMENTS INC·Filed 2002·Granted Mar 15, 2005·24 cites·7 claims
- 0482US9741718B2High voltage CMOS with triple gate oxideTEXAS INSTRUMENTS INC·Filed 2015·Granted Aug 22, 2017·3 cites·8 claims
- 0581US9401410B2Poly sandwich for deep trench fillTEXAS INSTRUMENTS INC·Filed 2014·Granted Jul 26, 2016·3 cites·13 claims
- 0678US6762130B2Method of photolithographically forming extremely narrow transistor gate elementsTEXAS INSTRUMENTS INC·Filed 2002·Granted Jul 13, 2004·23 cites·15 claims
- 0774US2024290844A1Carbon, nitrogen and/or fluorine co-implants for low resistance transistorsTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 0873US9865691B2Poly sandwich for deep trench fillTEXAS INSTRUMENTS INC·Filed 2017·Granted Jan 9, 2018·1 cites·13 claims
- 0973US8802577B2Method for manufacturing a semiconductor device using a nitrogen containing oxide layerNIIMI HIROAKI·Filed 2011·Granted Aug 12, 2014·3 cites·17 claims
- 1071US10714474B2High voltage CMOS with triple gate oxideTEXAS INSTRUMENTS INC·Filed 2017·Granted Jul 14, 2020·1 cites·14 claims
- 1166US12015057B2Carbon, nitrogen and/or fluorine co-implants for low resistance transistorsTEXAS INSTRUMENTS INC·Filed 2021·Granted Jun 18, 2024·0 cites·17 claims
- 1265US6583013B1Method for forming a mixed voltage circuit having complementary devicesTEXAS INSTRUMENTS INC·Filed 1999·Granted Jun 24, 2003·24 cites·13 claims
- 1363US7562333B2Method and process for generating an optical proximity correction model based on layout densityTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 14, 2009·7 cites·16 claims
- 1460US7569464B2Method for manufacturing a semiconductor device having improved across chip implant uniformityTEXAS INSTRUMENTS INC·Filed 2006·Granted Aug 4, 2009·2 cites·18 claims
- 1558US9054056B2Transistor performance using a two-step damage annealTEXAS INSTRUMENTS INC·Filed 2014·Granted Jun 9, 2015·0 cites·3 claims
- 1658US9029251B2Transistor performance using a two-step damage annealTEXAS INSTRUMENTS INC·Filed 2014·Granted May 12, 2015·0 cites·3 claims
- 1757US9583579B2Poly sandwich for deep trench fillTEXAS INSTRUMENTS INC·Filed 2016·Granted Feb 28, 2017·0 cites·7 claims
- 1854US8828855B2Transistor performance using a two-step damage annealNIIMI HIROAKI·Filed 2007·Granted Sep 9, 2014·0 cites·5 claims
- 1953US9117687B2High voltage CMOS with triple gate oxideTEXAS INSTRUMENTS INC·Filed 2012·Granted Aug 25, 2015·0 cites·13 claims
- 2052US2023154915A1Dual resistor integrationTEXAS INSTRUMENTS INC·Filed 2021·Application pending·0 cites
- 2146US2010032801A1Capacitor formed in interlevel dielectric layerTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 2245US7560779B2Method for forming a mixed voltage circuit having complementary devicesTEXAS INSTRUMENTS INC·Filed 2003·Granted Jul 14, 2009·2 cites·7 claims
- 2345US2007196970A1Method for manufacturing a semiconductor device using a nitrogen containing oxide layerTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
- 2444US2008268603A1Transistor performance using a two-step damage annealNIIMI HIROAKI·Filed 2007·Application pending·0 cites
- 2541US11121207B2Integrated trench capacitor with top plate having reduced voidsTEXAS INSTRUMENTS INC·Filed 2016·Granted Sep 14, 2021·0 cites·20 claims
- 2640US2019207010A1Silicide block integration for cmos technologyTEXAS INSTRUMENTS INC·Filed 2017·Application pending·0 cites
- 2739US10566200B2Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatingsTEXAS INSTRUMENTS INC·Filed 2018·Granted Feb 18, 2020·0 cites·20 claims
- 2836US2001046740A1Low cost solution to integrate two different mosfet designs on a chipFiled 2001·Application pending·0 cites
- 2933US2002052083A1Cost effective split-gate process that can independently optimize the low voltage(LV) and high voltage (HV) transistors to minimize reverse short channel effectsFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →