US2007196970A1PendingUtilityA1
Method for manufacturing a semiconductor device using a nitrogen containing oxide layer
Est. expiryFeb 21, 2026(expired)· nominal 20-yr term from priority
H10D 64/01354H10D 64/01344H10D 64/01332H10D 30/601H10D 84/0184H10D 84/0181H10D 84/038H10D 64/021H10D 30/0227
45
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Claims
Abstract
The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric, and forming a nitrided region over a sidewall of the nitrided gate dielectric.
Claims
exact text as granted — not AI-modified1 . A method for manufacturing a semiconductor device, comprising:
providing a gate structure over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric; and forming a nitride region in a sidewall of the nitrided gate dielectric.
2 . The method as recited in claim 1 wherein forming a nitride region includes subjecting the sidewall to a nitrogen containing plasma.
3 . The method as recited in claim 2 wherein the nitrogen containing plasma uses an RF plasma or a microwave plasma.
4 . The method as recited in claim 1 wherein forming a nitride region in the sidewall further includes forming a nitride region in sidewalls of the gate electrode.
5 . The method as recited in claim 1 further including subjecting the nitride region to a reoxidation step prior to forming a nitrogen containing oxide layer thereover.
6 . The method as recited in claim 5 wherein the reoxidation step uses a temperature ranging from about 400° C. to about 600° C. for a time period ranging from about 30 seconds to about 60 seconds.
7 . The method as recited in claim 1 further including forming a nitrogen containing oxide layer over the nitride region.
8 . The method as recited in claim 7 wherein forming the nitrogen containing oxide layer includes forming the nitrogen containing oxide layer by the oxynitridation of the nitride region in the presence of a nitrogen containing gas.
9 . The method as recited in claim 8 wherein the nitrogen containing gas is nitrous oxide (N 2 O) or nitric oxide (NO) or its mixtures.
10 . The method as recited in claim 7 wherein forming the nitrogen containing oxide layer over the nitride region further includes forming the nitrogen containing oxide layer over sidewalls of the gate electrode.
11 . The method as recited in claim 1 further including forming a dielectric layer having interconnects therein over the gate structure to form an operational integrated circuit.
12 . A semiconductor device, comprising:
a gate structure positioned over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric; and a nitride region located in a sidewall of the nitrided gate dielectric.
13 . The semiconductor device as recited in claim 12 wherein the nitride region has a thickness ranging from about 0.5 nm and about 1.0 nm.
14 . The semiconductor device as recited in claim 12 wherein the nitride region is further located in sidewalls of the gate electrode.
15 . The semiconductor device as recited in claim 12 further including a nitrogen containing oxide layer located over the nitride region.
16 . The semiconductor device as recited in claim 15 wherein the nitrogen containing oxide layer is further located over sidewalls of the gate electrode.
17 . The semiconductor device as recited in claim 15 wherein the nitrogen containing oxide layer has a thickness ranging from about 1.0 nm to about 1.5 nm.
18 . The semiconductor device as recited in claim 12 wherein edges of the nitrided gate dielectric have a higher concentration of nitrogen than a center of the nitrided gate dielectric.
19 . The semiconductor device as recited in claim 12 wherein edges of the nitrided gate dielectric have substantially the same concentration of nitrogen than a center of the nitrided gate dielectric.
20 . The semiconductor device as recited in claim 12 further including a dielectric layer having interconnects therein located over the gate structure.Join the waitlist — get patent alerts
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