Inventor · disambiguated record
Xian J. Ning
Also filed as: NING XIAN J · NING XIAN JIE
37 granted patents·2 pending applications·959 citations·filing 1997–2011
98Inventor score
Files withINFINEON TECHNOLOGIES AG14SEMICONDUCTOR MFG INT SHANGHAI11SIEMENS AG3INFINEON TECHNOLOGIES CORP2NING XIAN J2
Top patents by PatentIndex Score
39 records- 0196US6611453B2Self-aligned cross-point MRAM device with aluminum metallization layersINFINEON TECHNOLOGIES AG·Filed 2001·Granted Aug 26, 2003·122 cites·11 claims
- 0293US6692898B2Self-aligned conductive line for cross-point magnetic memory integrated circuitsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Feb 17, 2004·91 cites·15 claims
- 0392US6794262B2MIM capacitor structures and fabrication methods in dual-damascene structuresINFINEON TECHNOLOGIES AG·Filed 2002·Granted Sep 21, 2004·66 cites·32 claims
- 0491US6709874B2Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidationINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 23, 2004·74 cites·20 claims
- 0591US6451667B1Self-aligned double-sided vertical MIMcapINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 17, 2002·66 cites·35 claims
- 0690US6979526B2Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Dec 27, 2005·39 cites·22 claims
- 0790US6723600B2Method for making a metal-insulator-metal capacitor using plate-through mask techniquesIBM·Filed 2001·Granted Apr 20, 2004·49 cites·8 claims
- 0889US6620701B2Method of fabricating a metal-insulator-metal (MIM) capacitorINFINEON TECHNOLOGIES AG·Filed 2001·Granted Sep 16, 2003·56 cites·22 claims
- 0989US6440753B1Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive linesINFINEON TECHNOLOGIES CORP·Filed 2001·Granted Aug 27, 2002·48 cites·23 claims
- 1088US6815248B2Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processingINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 9, 2004·32 cites·28 claims
- 1185US7820500B2Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained siliconSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Oct 26, 2010·12 cites·20 claims
- 1285US7425488B2Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistorsSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted Sep 16, 2008·12 cites·17 claims
- 1384US7547595B2Integration scheme method and structure for transistors using strained siliconSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Jun 16, 2009·13 cites·20 claims
- 1484US6184134B1Dry process for cleaning residues/polymers after metal etchINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Feb 6, 2001·33 cites·12 claims
- 1581US7709336B2Metal hard mask method and structure for strained silicon MOS transistorsSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted May 4, 2010·8 cites·15 claims
- 1679US7591659B2Method and structure for second spacer formation for strained silicon MOS transistorsSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted Sep 22, 2009·9 cites·18 claims
- 1779US6780775B2Design of lithography alignment and overlay measurement marks on CMP finished damascene surfaceINFINEON TECHNOLOGIES AG·Filed 2001·Granted Aug 24, 2004·28 cites·16 claims
- 1878US5865901AWafer surface cleaning apparatus and methodSIEMENS AG·Filed 1997·Granted Feb 2, 1999·54 cites·25 claims
- 1977US6706588B1Method of fabricating an integrated circuit having embedded vertical capacitorINFINEON TECHNOLOGIES AG·Filed 2003·Granted Mar 16, 2004·24 cites·11 claims
- 2070US5903343AMethod for detecting under-etched viasSIEMENS AG·Filed 1997·Granted May 11, 1999·34 cites·29 claims
- 2168US7015110B2Method and structure of manufacturing high capacitance metal on insulator capacitors in copperSEMICONDUCTOR MFG INT SHANGHAI·Filed 2004·Granted Mar 21, 2006·14 cites·13 claims
- 2267US7335566B2Polysilicon gate doping method and structure for strained silicon MOS transistorsSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Feb 26, 2008·4 cites·20 claims
- 2366US7605470B2Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devicesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Oct 20, 2009·3 cites·19 claims
- 2463US7479699B2Seal ring structures with unlanded via stacksSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Jan 20, 2009·2 cites·28 claims
- 2562US8058120B2Integration scheme for strained source/drain CMOS using oxide hard maskNING XIAN JIE·Filed 2010·Granted Nov 15, 2011·3 cites·15 claims
- 2660US6677635B2Stacked MIMCap between Cu dual damascene levelsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Jan 13, 2004·11 cites·10 claims
- 2758US6960365B2Vertical MIMCap manufacturing methodINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 1, 2005·8 cites·20 claims
- 2856US6750115B1Method for generating alignment marks for manufacturing MIM capacitorsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 15, 2004·9 cites·52 claims
- 2956US6033984ADual damascene with bond padsSIEMENS AG·Filed 1997·Granted Mar 7, 2000·22 cites·17 claims
- 3052US6972251B2Method for fabricating copper damascene structures in porous dielectric materialsSEMICONDUCTOR MANUFACTORING IN·Filed 2003·Granted Dec 6, 2005·7 cites·13 claims
- 3151US6713395B2Single RIE process for MIMcap top and bottom platesINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 30, 2004·3 cites·19 claims
- 3248US8049308B2Bond pad for low K dielectric materials and method for manufacture for semiconductor devicesSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Nov 1, 2011·0 cites·20 claims
- 3347US8106423B2Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistorsWU HANMING·Filed 2008·Granted Jan 31, 2012·0 cites·18 claims
- 3445US8395240B2Bond pad for low K dielectric materials and method for manufacture for semiconductor devicesNING XIAN J·Filed 2011·Granted Mar 12, 2013·0 cites·19 claims
- 3545US8158520B2Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devicesNING XIAN J·Filed 2004·Granted Apr 17, 2012·3 cites·16 claims
- 3642US7663159B2Seal ring corner designSEMICONDUCTOR MFG INT SHANGHAI·Filed 2005·Granted Feb 16, 2010·0 cites·18 claims
- 3736US2003006480A1MIMCap with high dielectric constant insulatorFiled 2001·Application pending·0 cites
- 3835US8392863B2Method for circuit layout and rapid thermal annealing method for semiconductor apparatusJU JIANHUA·Filed 2010·Granted Mar 5, 2013·0 cites·16 claims
- 3931US2003113974A1Stacked metal-insulator-metal capacitor structures in between interconnection layersFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →