Stacked metal-insulator-metal capacitor structures in between interconnection layers

Abstract

A parallel capacitor structure that can be fabricated using advanced processing techniques that employ, for example, copper interconnects and low k dielectrics is described. The parallel capacitor structure includes a first copper dual Damascene interconnection line, a first interconnection, a middle capacitor electrode, a dielectric layer, a second interconnection, an upper capacitor electrode, and a second interlayer dielectric layer. The existing first copper dual Damascene interconnection line is embedded in a first interlayer dielectric layer, and is utilized as a lower capacitor electrode. The middle capacitor electrode is on the first copper dual Damascene interconnection line. The dielectric layer is interposed between the first copper dual Damascene interconnection line and the middle capacitor electrode. The second interconnection can be directly connected to the middle capacitor electrode. The first interconnection connects the upper capacitor electrode to the first copper dual Damascene interconnection line. The second interlayer dielectric layer is interposed between the middle capacitor electrode and the upper capacitor electrode. When a potential having a first polarity is applied to the upper capacitor electrode and to the first copper dual Damascene interconnection line, and a potential having a second polarity, opposite the first polarity, is applied to the middle capacitor electrode, this structure functions as a parallel capacitor. By using an existing first copper dual Damascene interconnection line as a lower capacitor electrode, the capacitance per unit area can be increased without substantially increasing manufacturing complexity.

What is claimed is:  
     
         1 . A method of forming an integrated circuit, comprising: 
 providing a first interlayer dielectric layer;    forming a first trench and a via in the first interlayer dielectric layer and filling the first trench and via with a conductor to provide lower capacitor electrode;    depositing a dielectric film;    providing a patterned a middle capacitor electrode; and    providing a patterned second interlayer dielectric layer having a first via, a second via, and an upper capacitor electrode, wherein the upper capacitor electrode is connected to the lower capacitor electrode by the first via, and wherein the second via is connected to the middle capacitor electrode.    
     
     
         2 . A method of according to  claim 1 , wherein the lower capacitor electrode has a copper surface coplanar with a surface of the first interlayer dielectric layer laterally surrounding the lower capacitor electrode.  
     
     
         3 . A method of according to  claim 1 , wherein the upper capacitor electrode is surrounded laterally by the second interlayer dielectric layer and has a substantially planar face separated from at least a portion of the middle capacitor electrode by the second interlayer dielectric layer.  
     
     
         4 . A method of according to  claim 1 , wherein the conductor is copper.  
     
     
         5 . A method of according to  claim 1 , wherein the lower capacitor electrode comprises a first copper dual Damascene interconnection line adapted to be used as an electrode.  
     
     
         6 . A method of according to  claim 1 , wherein the upper capacitor electrode comprises a an interconnection line adapted to be used as an electrode.  
     
     
         7 . A method of according to  claim 6 , wherein the upper capacitor electrode comprises a copper Damascene interconnection line.  
     
     
         8 . A method of according to  claim 1 , wherein the middle capacitor electrode is located between the lower capacitor electrode and the upper capacitor electrode.  
     
     
         9 . A method of according to  claim 1 , wherein the lower capacitor electrode and the upper capacitor electrode are located between the first via and the second via.  
     
     
         10 . A method of according to  claim 1 , wherein the lower capacitor electrode includes a via portion and a line portion.  
     
     
         11 . A method of according to  claim 1 , forming a first trench and a via in the first interlayer dielectric layer and filling the first trench and via with a conductor to provide lower capacitor electrode, comprises: 
 providing a first patterned mask on the first interlayer dielectric layer;    etching away portions of the first interlayer dielectric layer to form a groove therein;    removing the first patterned mask from the surface to the first interlayer dielectric layer to form the via;    providing a second patterned mask on the first interlayer dielectric layer;    etching away other portions of the first interlayer dielectric layer to thereby form a trench over the via in the first interlayer dielectric layer;    depositing a first conductive layer consisting essentially of copper; and    chemical mechanical polishing the first conductive layer until the first conductive layer is coplanar with a surface of the first interlayer dielectric layer, wherein the remaining portions of the first conductive layer comprise the lower capacitor electrode adapted to serve as a bottom capacitor electrode of a first capacitor structure.    
     
     
         12 . The method according to  claim 11 , wherein depositing a first conductive layer consisting essentially of copper: 
 depositing a liner layer;    forming a copper seed layer on the liner layer; and    electroplating copper within the trench to define, at least in part, a lower capacitor electrode.    
     
     
         13 . A method of according to  claim 1 , wherein depositing a dielectric film comprises: 
 plasma enhanced chemical vapor depositing a silicon nitride dielectric film having a thickness between 500 Å and 1500 Å.    
     
     
         14 . A method of according to  claim 1 , wherein providing a patterned a middle capacitor electrode on the lower capacitor electrode comprises: 
 depositing a second conductive layer;    providing a mask pattern on the second conductive layer; and    etching the second conductive layer such that the remaining portion of the second conductive layer comprises a middle capacitor electrode.    
     
     
         15 . A method of according to  claim 14 , wherein the second conductive layer comprises a metal selected from the group consisting of TiN, W, TaN, Al, Cu, Ta, and Ti.  
     
     
         16 . A method of according to  claim 14 , wherein a thickness of the second conductive layer is substantially equal to a thickness of the dielectric film.  
     
     
         17 . A method of according to  claim 15 , wherein the second conductive layer has a thickness between 400 Å and 1500 Å.  
     
     
         18 . A method of according to  claim 14 , wherein etching the second conductive layer such that the remaining portion of the second conductive layer comprises a middle capacitor electrode comprises: 
 reactive-ion etching the second conductive layer such that the remaining portion of the second conductive layer comprises a middle capacitor electrode, wherein the middle capacitor electrode is adapted to serve as an upper electrode of a first capacitor structure and a lower electrode of a second capacitor structure.    
     
     
         19 . A method of according to  claim 1 , wherein providing a patterned a middle capacitor electrode is followed by the step of: 
 depositing a dielectric layer.    
     
     
         20 . A method of according to  claim 19 , wherein depositing a dielectric layer, comprises: 
 depositing a silicon nitride layer having a thickness between 500 Å and 1500 Å.    
     
     
         21 . A method of according to  claim 1 , wherein providing a patterned second interlayer dielectric layer, comprises the steps of: 
 providing a second interlayer dielectric layer;    providing a third patterned mask on the second interlayer dielectric layer;    etching away portions of the second interlayer dielectric layer to form a first via opening and a second via opening therein;    removing the third patterned mask from the surface to the second interlayer dielectric layer;    providing a fourth patterned mask on the second interlayer dielectric layer;    etching away other portions of the second interlayer dielectric layer to form a upper capacitor electrode opening therein;    removing the fourth patterned mask from the surface to the second interlayer dielectric layer;    depositing a third conductive layer to simultaneously fill the first via opening, the second via opening, and the upper capacitor electrode opening; and    planarizing the third conductive layer until a surface of the third conductive layer is coplanar with a surface of the second interlayer dielectic layer such that the remaining portions comprise and a upper capacitor electrode, a first via connected to the lower capacitor electrode and the upper capacitor electrode, and a second via connected to the middle electrode plate.    
     
     
         22 . The method according to  claim 21 , wherein depositing a third conductive layer, comprises: 
 depositing a liner layer;    forming a copper seed layer on the liner layer; and    electroplating copper within the trench to define, at least in part, a lower capacitor electrode.    
     
     
         23 . A method of according to  claim 21 , wherein the second interlayer dielectric layer has a thickness between 3000 Å and 7000 Å.  
     
     
         24 . A method of according to  claim 21 , wherein the third conductive layer consists essentially of copper.  
     
     
         25 . A method of according to  claim 1 , wherein providing a patterned second interlayer dielectric layer having a first via, a second via, and a second interconnection line embedded therein, wherein the second interconnection line is connected to the lower capacitor electrode by the first via, and wherein the second via is connected to the middle capacitor electrode, comprises the steps of: 
 providing a second interlayer dielectric layer;    providing a third patterned mask on the second interlayer dielectric layer;    etching away portions of the second interlayer dielectric layer to form a first via opening to the lower capacitor electrode and a second via opening to the middle capacitor electrode;    removing the third patterned mask from the surface to the second interlayer dielectric layer;    chemical vapor depositing a third conductive layer to simultaneously fill the first via opening and the second via opening; and    planarizing the third conductive layer until the third conductive layer is flush with a surface of the second interlayer dielectric layer such that the remaining portions comprise a first via connected to the lower capacitor electrode, and a second via connected to the middle capacitor electrode;    providing a fourth conductive layer;    providing a fourth patterned mask on the fourth conductive layer;    reactive ion etching away portions of the fourth conductive layer such that remaining portions of the fourth conductive layer comprise a first interconnection connected to the first via, a top capacitor electrode on the middle capacitor electrode, and a second interconnection connected to the second via;    removing the fourth patterned mask; and    depositing a third interlayer dielectric layer to simultaneously fill spaces adjacent the first interconnection, the top capacitor electrode, and the second interconnection.    
     
     
         26 . A method of according to  claim 25 , wherein the third conductive layer consists essentially of tungsten.  
     
     
         27 . A method of according to  claim 25 , wherein the fourth conductive layer consists essentially of aluminum.  
     
     
         28 . A method of according to  claim 25 , wherein planarizing the third conductive layer until the third conductive layer is flush with a surface of the second interlayer dielectic layer comprises: 
 chemical mechanical polishing the third conductive layer until the third conductive layer is flush with a surface of the second interlayer dielectic layer.    
     
     
         29 . An integrated circuit, comprising: 
 a lower capacitor electrode having a copper surface coplanar with a surface of a first interlayer dielectric layer laterally surrounding the lower capacitor electrode;    a first conductive via;    a middle capacitor electrode on the lower capacitor electrode;    a dielectric layer interposed between the lower capacitor electrode and the middle capacitor electrode;    a second conductive via directly connected to the middle capacitor electrode;    an upper capacitor electrode surrounded laterally by the second interlayer dielectric layer, wherein the first conductive via connects the upper capacitor electrode to the lower capacitor electrode; and    a second interlayer dielectric layer interposed between the middle capacitor electrode and the upper capacitor electrode.    
     
     
         30 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode includes a substantially planar face separated from at least a portion of the middle capacitor electrode by the dielectric layer.  
     
     
         31 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode comprises a copper dual Damascene interconnection line.  
     
     
         32 . An integrated circuit according to  claim 31 , wherein the upper capacitor electrode comprises a copper Damascene interconnection line.  
     
     
         33 . An integrated circuit according to  claim 31 , wherein the middle capacitor electrode is located within a region defined by the copper dual Damascene interconnection line and upper capacitor electrode.  
     
     
         34 . An integrated circuit according to  claim 32 , wherein the middle capacitor electrode is located within a region defined by the copper dual Damascene interconnection line and the copper Damascene interconnection line.  
     
     
         35 . An integrated circuit according to  claim 29 , wherein the upper capacitor electrode comprises aluminum.  
     
     
         36 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode, middle capacitor electrode, and upper capacitor electrode are each located within a region defined by the first conductive via and the second conductive via.  
     
     
         37 . An integrated circuit according to  claim 35 , wherein the first conductive via comprises a tungsten contact and a aluminum plug.  
     
     
         38 . An integrated circuit according to  claim 35 , wherein the second conductive via comprises a tungsten contact and an aluminum plug, wherein the tungsten contact is directly coupled to the middle capacitor electrode.  
     
     
         39 . An integrated circuit according to  claim 29 , wherein the middle capacitor electrode is located between the first conductive via, the second conductive via, the lower capacitor electrode, and the upper capacitor electrode.  
     
     
         40 . An integrated circuit according to  claim 32 , wherein the middle capacitor electrode is located within a region defined by the first conductive via, the second conductive via, the lower capacitor electrode, and the copper Damascene interconnection line.  
     
     
         41 . An integrated circuit according to  claim 29 , wherein the upper capacitor electrode consists essentially of copper.  
     
     
         42 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode consists essentially of copper.  
     
     
         43 . An integrated circuit according to  claim 29 , wherein the middle capacitor electrode comprises a metal selected from the group consisting of TiN, W, TaN, Al, Cu, Ta, and Ti.  
     
     
         44 . An integrated circuit according to  claim 29 , wherein the upper capacitor electrode has a thickness between 1000 and 10000 Å.  
     
     
         45 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode has a thickness between 1500 and 4000 Å.  
     
     
         46 . An integrated circuit according to  claim 29 , wherein the middle capacitor electrode has a thickness between 300 and 1500 Å.  
     
     
         47 . An integrated circuit according to  claim 29 , wherein the lower capacitor electrode, the dielectric layer, and the middle capacitor electrode comprise a first capacitor structure.  
     
     
         48 . An integrated circuit according to  claim 29 , wherein the middle capacitor electrode, second interlayer dielectric layer, and upper capacitor electrode comprise a second capacitor structure.  
     
     
         49 . An integrated circuit, comprising: 
 a lower capacitor electrode having a copper surface coplanar with a surface of a first interlayer dielectric layer laterally surrounding the lower capacitor electrode;    a capacitor dielectric layer extending over at least a portion of the copper surface of the lower capacitor electrode and extending over at least a portion of the first interlayer dielectric layer;    a middle capacitor electrode;    a second interlayer dielectric layer over at least a portion of the capacitor dielectric layer and the middle capacitor electrode; and    an upper capacitor electrode surrounded laterally by the second interlayer dielectric layer.