Inventor · disambiguated record
Thomas W. Dyer
Also filed as: DYER THOMAS · DYER THOMAS W · DYER THOMAS WALTER
94 granted patents·21 pending applications·817 citations·filing 2000–2015
99Inventor score
Files withIBM89DYER THOMAS W8INFINEON TECHNOLOGIES AG3SAMSUNG ELECTRONICS CO LTD3GLOBALFOUNDRIES INC2
Top patents by PatentIndex Score
115 records- 0198US7816231B2Device structures including backside contacts, and methods for forming sameIBM·Filed 2006·Granted Oct 19, 2010·55 cites·6 claims
- 0296US7485520B2Method of manufacturing a body-contacted finfetIBM·Filed 2007·Granted Feb 3, 2009·55 cites·1 claims
- 0394US7964910B2Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structureIBM·Filed 2007·Granted Jun 21, 2011·20 cites·8 claims
- 0494US7911001B2Methods for forming self-aligned dual stress liners for CMOS semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Mar 22, 2011·29 cites·13 claims
- 0593US7485508B2Two-sided semiconductor-on-insulator structures and methods of manufacturing the sameIBM·Filed 2007·Granted Feb 3, 2009·28 cites·20 claims
- 0693US7101744B1Method for forming self-aligned, dual silicon nitride liner for CMOS devicesIBM·Filed 2005·Granted Sep 5, 2006·28 cites·20 claims
- 0792US8889504B2Semiconductor devices having tensile and/or compressive stress and methods of manufacturingDYER THOMAS W·Filed 2012·Granted Nov 18, 2014·9 cites·9 claims
- 0892US7741188B2Deep trench (DT) metal-insulator-metal (MIM) capacitorIBM·Filed 2008·Granted Jun 22, 2010·41 cites·16 claims
- 0990US7482215B2Self-aligned dual segment liner and method of manufacturing the sameIBM·Filed 2006·Granted Jan 27, 2009·20 cites·14 claims
- 1089US7569489B2High performance 3D FET structures, and methods for forming the same using preferential crystallographic etchingIBM·Filed 2007·Granted Aug 4, 2009·12 cites·14 claims
- 1189US6897107B2Method for forming TTO nitride liner for improved collar protection and TTO reliabilityINFINEON TECHNOLOGIES CORP·Filed 2003·Granted May 24, 2005·38 cites·10 claims
- 1287US9455186B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Sep 27, 2016·4 cites·1 claims
- 1387US8697528B2Method of forming a planar field effect transistor structure with recesses for epitaxially deposited source/drain regionsDYER THOMAS W·Filed 2012·Granted Apr 15, 2014·6 cites·16 claims
- 1487US7488659B2Structure and methods for stress concentrating spacerIBM·Filed 2007·Granted Feb 10, 2009·29 cites·1 claims
- 1586US8685806B2Silicon-on-insulator substrate with built-in substrate junctionIBM·Filed 2013·Granted Apr 1, 2014·6 cites·20 claims
- 1686US7635899B2Structure and method to form improved isolation in a semiconductor deviceIBM·Filed 2007·Granted Dec 22, 2009·14 cites·7 claims
- 1786US7488660B2Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structureIBM·Filed 2006·Granted Feb 10, 2009·13 cites·10 claims
- 1885US8377785B2Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structureIBM·Filed 2011·Granted Feb 19, 2013·5 cites·16 claims
- 1985US7790542B2CMOS devices having reduced threshold voltage variations and methods of manufacture thereofIBM·Filed 2008·Granted Sep 7, 2010·12 cites·11 claims
- 2084US7566949B2High performance 3D FET structures, and methods for forming the same using preferential crystallographic etchingIBM·Filed 2006·Granted Jul 28, 2009·8 cites·10 claims
- 2184US6335248B1Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technologyIBM·Filed 2001·Granted Jan 1, 2002·37 cites·22 claims
- 2283US7955940B2Silicon-on-insulator substrate with built-in substrate junctionIBM·Filed 2009·Granted Jun 7, 2011·8 cites·13 claims
- 2383US7666721B2SOI substrates and SOI devices, and methods for forming the sameIBM·Filed 2006·Granted Feb 23, 2010·10 cites·14 claims
- 2482US7582516B2CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxyIBM·Filed 2006·Granted Sep 1, 2009·10 cites·18 claims
- 2582US7528451B2CMOS gate conductor having cross-diffusion barrierIBM·Filed 2007·Granted May 5, 2009·9 cites·20 claims
- 2681US8896069B2Semiconductor devices having tensile and/or compressive stress and methods of manufacturingDYER THOMAS W·Filed 2012·Granted Nov 25, 2014·3 cites·3 claims
- 2781US7884448B2High performance 3D FET structures, and methods for forming the same using preferential crystallographic etchingIBM·Filed 2009·Granted Feb 8, 2011·6 cites·14 claims
- 2881US7452758B2Process for making FinFET device with body contact and buried oxide junction isolationIBM·Filed 2007·Granted Nov 18, 2008·9 cites·2 claims
- 2980US8293631B2Semiconductor devices having tensile and/or compressive stress and methods of manufacturingDYER THOMAS W·Filed 2008·Granted Oct 23, 2012·4 cites·10 claims
- 3080US8198194B2Methods of forming p-channel field effect transistors having SiGe source/drain regionsYANG JONG HO·Filed 2010·Granted Jun 12, 2012·8 cites·11 claims
- 3180US7910451B2Simultaneous buried strap and buried contact via formation for SOI deep trench capacitorIBM·Filed 2008·Granted Mar 22, 2011·8 cites·20 claims
- 3280US7736966B2CMOS devices with hybrid channel orientations and method for fabricating the sameIBM·Filed 2008·Granted Jun 15, 2010·7 cites·11 claims
- 3379US9385038B2Selective local metal cap layer formation for improved electromigration behaviorIBM·Filed 2015·Granted Jul 5, 2016·2 cites·6 claims
- 3479US7750429B2Self-aligned and extended inter-well isolation structureIBM·Filed 2007·Granted Jul 6, 2010·6 cites·11 claims
- 3579US7456450B2CMOS devices with hybrid channel orientations and method for fabricating the sameIBM·Filed 2006·Granted Nov 25, 2008·7 cites·8 claims
- 3679US7436030B2Strained MOSFETs on separated silicon layersIBM·Filed 2006·Granted Oct 14, 2008·8 cites·12 claims
- 3778US7728364B2Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolationIBM·Filed 2007·Granted Jun 1, 2010·7 cites·11 claims
- 3878US7598540B2High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the sameIBM·Filed 2006·Granted Oct 6, 2009·6 cites·8 claims
- 3978US7485516B2Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formationIBM·Filed 2005·Granted Feb 3, 2009·7 cites·16 claims
- 4078US7122437B2Deep trench capacitor with buried plate electrode and isolation collarIBM·Filed 2003·Granted Oct 17, 2006·23 cites·26 claims
- 4178US6809368B2TTO nitride liner for improved collar protection and TTO reliabilityIBM·Filed 2001·Granted Oct 26, 2004·15 cites·4 claims
- 4277US7808082B2Structure and method for dual surface orientations for CMOS transistorsIBM·Filed 2006·Granted Oct 5, 2010·5 cites·16 claims
- 4377US7517767B2Forming conductive stud for semiconductive devicesIBM·Filed 2006·Granted Apr 14, 2009·6 cites·3 claims
- 4477US7393746B2Post-silicide spacer removalIBM·Filed 2006·Granted Jul 1, 2008·6 cites·6 claims
- 4576US8063449B2Semiconductor devices and methods of manufacture thereofHAN JIN-PING·Filed 2009·Granted Nov 22, 2011·6 cites·22 claims
- 4676US7968910B2Complementary field effect transistors having embedded silicon source and drain regionsIBM·Filed 2008·Granted Jun 28, 2011·6 cites·10 claims
- 4776US7550330B2Deep junction SOI MOSFET with enhanced edge body contactsIBM·Filed 2006·Granted Jun 23, 2009·6 cites·10 claims
- 4875US7667255B2Deep trench inter-well isolation structureIBM·Filed 2007·Granted Feb 23, 2010·6 cites·9 claims
- 4975US7442614B1Silicon on insulator devices having body-tied-to-source and methods of makingIBM·Filed 2008·Granted Oct 28, 2008·4 cites·4 claims
- 5074US7560382B2Embedded interconnects, and methods for forming sameIBM·Filed 2006·Granted Jul 14, 2009·5 cites·8 claims
Showing the top 50 of 115 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →