Inventor · disambiguated record
Vicente Enrique Chung
Also filed as: CHUNG VICENTE E · CHUNG VICENTE ENRIQUE
16 granted patents·3 pending applications·230 citations·filing 1999–2008
94Inventor score
Files withIBM19
Top patents by PatentIndex Score
19 records- 0196US7469318B2System bus structure for large L2 cache array topology with different latency domainsIBM·Filed 2005·Granted Dec 23, 2008·46 cites·6 claims
- 0284US7308558B2Multiprocessor data processing system having scalable data interconnect and data routing mechanismIBM·Filed 2004·Granted Dec 11, 2007·39 cites·17 claims
- 0379US7380102B2Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined responseIBM·Filed 2005·Granted May 27, 2008·8 cites·5 claims
- 0478US7627738B2Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another nodeIBM·Filed 2007·Granted Dec 1, 2009·7 cites·8 claims
- 0575US7308536B2System bus read data transfers with data ordering control bitsIBM·Filed 2005·Granted Dec 11, 2007·6 cites·12 claims
- 0674US6865695B2Robust system bus recoveryIBM·Filed 2001·Granted Mar 8, 2005·20 cites·25 claims
- 0761US8015358B2System bus structure for large L2 cache array topology with different latency domainsIBM·Filed 2008·Granted Sep 6, 2011·1 cites·15 claims
- 0860US7526631B2Data processing system with backplane and processor books configurable to support both technical and commercial workloadsIBM·Filed 2003·Granted Apr 28, 2009·6 cites·4 claims
- 0959US6581116B1Method and apparatus for high performance transmission of ordered packets on a bus within a data processing systemIBM·Filed 1999·Granted Jun 17, 2003·34 cites·15 claims
- 1057US6360297B1System bus read address operations with data ordering preference hint bits for vertical cachesIBM·Filed 1999·Granted Mar 19, 2002·31 cites·26 claims
- 1154US7007128B2Multiprocessor data processing system having a data routing mechanism regulated through control communicationIBM·Filed 2004·Granted Feb 28, 2006·3 cites·14 claims
- 1253US2008209163A1Data processing system with backplane and processor books configurable to suppprt both technical and commercial workloadsIBM·Filed 2008·Application pending·0 cites
- 1352US7793048B2System bus structure for large L2 cache array topology with different latency domainsIBM·Filed 2008·Granted Sep 7, 2010·0 cites·11 claims
- 1445US2004236891A1Processor book for building large scalable processor systemsIBM·Filed 2003·Application pending·0 cites
- 1542US2006179197A1Data processing system, method and interconnect fabric having a partial response rebroadcastIBM·Filed 2005·Application pending·0 cites
- 1638US6535957B1System bus read data transfers with bus utilization based data orderingIBM·Filed 1999·Granted Mar 18, 2003·9 cites·21 claims
- 1737US6487679B1Error recovery mechanism for a high-performance interconnectIBM·Filed 1999·Granted Nov 26, 2002·8 cites·20 claims
- 1836US6349360B1System bus read address operations with data ordering preference hint bitsIBM·Filed 1999·Granted Feb 19, 2002·8 cites·17 claims
- 1933US6874063B1System bus read data transfers with data ordering control bitsIBM·Filed 1999·Granted Mar 29, 2005·4 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →