Data processing system with backplane and processor books configurable to suppprt both technical and commercial workloads

Abstract

A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

1 . A data processing system comprising:
 a processor book configured on a motherboard, wherein said processor book includes:
 a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S 0  and T 0 ; 
   a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S 1  and T 1 ;   a third set of buses external to said first processor chip module and said second processor chip module and which interconnect each of processor chips S 0  and T 0  a respective one of processor chips S 1 , and T 1 ; and   a fourth set of buses extending externally from the outer physical perimeter edge of the motherboard of said processor book, said fourth set of buses including a plurality of external routing buses each connected to a respective processor chip in said processor book, wherein said external routing buses provide a connection point for components external to the processor book;   means for selectively connecting an external routing bus of one processor chip of said first processor chip module to an external routing bus of a processor chip of said second processor chip module, wherein said means for selectively connecting connects the external routing bus of the one processor chip of the first processor chip module to the external routing bus of the processor chip of the second processor chip module when the processor book is to be utilized to process technical workloads, said means for connecting directly connects each chip of the first processor chip module to a chip of the second processor chip module that is a largest number of processor hops away from the chip of the first processor chip module; and   distributed routing logic located on each processor chip of both the first processor chip module and the second processor chip module, said distributed routing logic comprising:
 first routing protocol for routing data among processor chips of both the first processor chip module and the second processor chip module without utilizing any of said external routing buses; 
 second routing protocol for routing data among said processor chips of both the first processor chip module and the second processor chip module of said processor book utilizing said external routing bus, when said external routing bus is selectively wired to another processor chip in said processor book to produce a technical workbook configuration; and 
 selection mechanism for selecting between said first routing protocol and said second routing protocol for said processor book. 
   
   
   
       2 . The data processing system of  claim 1 , wherein one bus of said external routing buses is an external connector bus (ECB). 
   
   
       3 . The data processing system of  claim 1 , wherein one bus of said external routing bus is an input/output (I/O) bus. 
   
   
       4 . The data processing system of  claim 3 , wherein said first and second modules are interconnected to provide a first processor book, and said first processor book comprises a plurality of external connector buses (ECB) each providing an external wire connection to and from each chip, wherein further said data processing system includes:
 a second processor book also having ECBs and connected to said first processor book via said ECBs, wherein said second processor book comprises I/O buses and said I/O buses of said second processor book are utilized for standard I/O operations for both said first and second processor books; and   means for controlling data transmission between said first and second modules within both said first processor book and said second processor book to enable the data processing system to support commercial workloads at said second processor book while supporting technical workloads at said first processor book.   
   
   
       5 . The data processing system of  claim 1 , wherein:
 said first and said second modules both include identical configurations of first, second, third and fourth processor chips coupled sequentially by said first set of buses; and   said connecting directly connects:   first chip of first module to third chip of second module;   second chip of first module to fourth chip of second module;   third chip of first module to first chip of second module;   fourth chip of first module to second chip of second module;   first chip of second module to third chip of first module;   second chip of second module to fourth chip of first module;   third chip of second module to first chip of first module;   fourth chip of second module to second chip of first module;   
   
   
       6 . The data processing system of  claim 1 , further comprising:
 distributed routing logic for controlling efficient data transmission by selecting among multiple paths including a direct path along one bus of the external routing buses wired from a source processor chip to a destination processor chip, wherein said distributed routing logic is configured as individual blocks of logic on each of said processor chips of said processor book, and each block of logic controls routing of transmission from its respective processor chip.   
   
   
       7 . The data processing system of  claim 6 , further comprising:
 a default logic that routes transmissions from one processor chip to a next processor chip of said processor book without utilizing said external routing bus;   a specific routing logic that accounts for an additional path provided by a wiring of one bus of said external routing buses during route selection;   means for determining when said processor chips are correctly wired via said external routing buses to provide an additional path for data transmission; and   means, responsive to said determination, for automatically initiating the specific routing logic.   
   
   
       8 . The data processing system of  claim 7 , further comprising:
 means, when the external routing buses of said processor chips are not wired according to a pre-set technical workload wiring scheme, for automatically initiating said default logic, wherein transmissions are routed without utilizing said additional path provided via the external routing buses.   
   
   
       9 . The data processing system of  claim 7 , wherein said fourth set of buses includes input/output (I/O) buses, said data processing system further comprising:
 an output mechanism;   means, when the external routing buses of said processor chips are not wired according to a pre-set wiring scheme, for generating a message indicating an error in wiring; and   means for forwarding said message to the output mechanism.   
   
   
       10 . The data processing system of  claim 6 , wherein said distributed routing logic further comprises:
 a first routing logic applicable for commercial workloads that utilizes only said third set of buses to route cross-transmissions between a processor chip of said first module and a corresponding processor chip of said second module;   a second routing logic applicable to handling operation of the system for technical workloads by utilizing the additional direct routing path provided by the wiring of the external routing bus;   a selection mechanism having a first selection indicating processor book operation for commercial workloads and a second selection indicating processor book operation for technical workloads; and   means, responsive to said selection mechanism providing said first selection, for initiating the first routing logic, and when said selection mechanism provides said second selection, initiating the second routing logic.   
   
   
       11 . The data processing system of  claim 10 , wherein said selection mechanism is a mode bit that has a setable value of 1 or 0 respectively indicating a particular one of processor book operation for commercial workload and processor book operation for technical workload. 
   
   
       12 . The data processing system of  claim 10 , wherein said selection mechanism is a latch that is setable to a high or low value respectively indicating a particular one of processor book operation for commercial workload and processor book operation for technical workload. 
   
   
       13 . The data processing system of  claim 10 , wherein said selection mechanism includes the operating system and hypervisor that dynamically triggers one of said first or second selections. 
   
   
       14 . The data processing system of  claim 10 , further comprising means for setting a value of said selection mechanism during Power-On Reset. 
   
   
       1615 . The data processing system of  claim 1 , wherein each of said external routing buses is directly wired to a destination processor chip that is a largest number of processor hops away from the source processor chip from which said external routing bus originates, such that a direct routing path is provided for transmissions from said source processor chip to said destination processor chip, and wherein further said direct routing path provides an alternate routing path and thus increased bandwidth to standard routing paths already available. 
   
   
       16 . A data processing system comprising:
 a system rack including a backplane with a plurality of receptors for receiving a plug-in head of processor books that are configured with MCMs having ECBs terminating within the plug-in head, wherein each receptor of said plurality of receptor are wired sequentially to each other;   a first processor book configured on a motherboard and having said plug-in head coupled to a first one of said plurality of receptors, said first processor book comprising:
 a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S 0  and T 0 ; 
 a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S 1  and T 1 ; 
 a third set of buses external to said first processor chip module and said second processor chip module and which interconnect each of processor chips S 0  and T 0  a respective one of processor chips S 1 , and T 1 ; 
 a fourth set of buses extending externally from the outer physical perimeter edge of the motherboard of said processor book, said fourth set of buses including a plurality of external routing buses each connected to a respective processor chip in said processor book, wherein said external routing buses provide a connection point for components external to the processor book; and 
 means for connecting the fourth set of buses to from a first processor chip of said processor book to another processor chip of said processor book, wherein when the processor book is being utilized to process technical workload, said means is selectively utilized to connect each processor chip of both the first processor chip module and the second processor chip module to another processor chip on the processor book that is a largest number of processor hops away. 
   
   
   
       17 . The data processing system of  claim 16 , said first processor book further comprising:
 a distributed memory with individual memory components externally coupled to each of said processor chips of said first and said second processor chip modules; and   wherein said first, second, third, and fourth set of buses enable full access to each of said individual memory components by each processor within said processor chips without memory affinity.   
   
   
       18 . The data processing system of  claim 16 , further comprising:
 a second processor book coupled to a second one of said plurality of receptors, said second processor book similarly configured to said first processor book and capable of interconnecting with said first processor book; and   means for interconnecting said fourth set of buses of said first processor book to similar busses of said second processor book via the backplane to enable expansion of the processing power of the data processing system for use as a commercial workload system.   
   
   
       19 . The data processing system of  claim 18 , further comprising:
 wiring means for completing a connection from one receptor to another when said receptor does not contain a processor book coupled thereto so that a complete connection path is always provided within said system rack.   
   
   
       20 . The data processing system of  claim 18 , further comprising:
 wiring means for completing a connection from one receptor to another when said receptor contains a processor book wired as a technical workload processor book, so that a complete connection path is provided within said system rack supporting both said technical workload processor book and any other processor book coupled thereto, wherein said wiring means directly connects each of said external routing buses to a destination processor chip that is a largest number of processor hops away from the source processor chip from which said external routing bus originates.   
   
   
       21 . The data processing system of  claim 16 , wherein further, said fourth set of buses extend from said first processor chip into said plug-in head and terminate as bus connectors within said plug-in head. 
   
   
       22 . The data processing system of  claim 18 , wherein:
 said plug-in head further comprises:
 a first wired routing path that routes communication received at the plug-in head in and out of said first processor book to a component of said system rack via said receptor; 
 a second wired routing path that routes communication received at the plug-in head from the first processor book back to a selected chip of said first processor book based on a preset wiring scheme designed for technical workload processor books, wherein said wiring means directly connects each of said external routing buses to a destination processor chip that is a largest number of processor hops away from the source processor chip from which said external routing bus originates; and 
 said backplane comprises selection logic for selecting between said first wired routing path and said second wired routing path and routing communication from processor chips of the processor book connected to the plug-in head according to the selected path. 
   
   
   
       23 . The data processing system of  claim 22 , wherein said logic includes a software-enabled selection mechanism, dynamically settable by software. 
   
   
       24 . The data processing system of  claim 22 , wherein said logic includes a physical selection mechanism settable by physical user selection. 
   
   
       25 . A data processing system comprising:
 a system rack including a backplane with a plurality of receptors for receiving a plug-in head of processor books that are configured with MCMs having ECBs terminating within the plug-in head, wherein each receptor of said plurality of receptor are wired sequentially to each other;   a first processor book configured on a motherboard and having said plug-in head coupled to a first one of said plurality of receptors, said first processor book comprising:
 a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S 0  and T 0 ; 
 a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S 1  and T 1 ; 
 a third set of buses external to said first processor chip module and said second processor chip module and which interconnect each of processor chips S 0  and T 0  a respective one of processor chips S 1 , and T 1 ; and 
 a fourth set of buses extending externally from the outer physical perimeter edge of the motherboard of said processor book, said fourth set of buses including a plurality of external routing buses each connected to a respective processor chip in said processor book, wherein said external routing buses provide a connection point for components external to the processor book; and 
 an add-on connector coupled to said first receptor, said add-on connector being a separate component from the first receptor and comprising a receptor end for receiving said plug-in head of said first processor book and a plug-in end for coupling said add-on connector to said first receptor, wherein said first processor book is coupled to the first receptor via the add-on connector to enable the first processor book to be utilized as a technical workbook, wherein said add-on connector further comprises:
 a first wired routing path that routes communication received at the receptor end from the first processor book out to said system rack via said plug-in end coupled to said receptor; 
 a second wired routing path that routes communication received at the receptor end from the first processor book back to a selected chip of said first processor book based on a preset wiring scheme designed for technical workload processor books, wherein each of said external routing buses is directly wired to a destination processor chip that is a largest number of processor hops away from a source processor chip from which said external routing bus originates, such that a direct routing path is provided for transmissions from said source processor chip to said destination processor chip; and 
 logic for selecting between said first wired routing path and said second wired routing path and routing communication according to the selected wired routing path. 
 
   
   
   
       26 . The data processing system of  claim 25 , wherein said logic includes a MUX with a selection mechanism dynamically settable by software. 
   
   
       27 . The data processing system of  claim 25 , wherein said logic includes a MUX with a physical selection mechanism settable by user selection. 
   
   
       28 . The data processing system of  claim 16 , wherein further each receptor comprises:
 logic for selecting between a first routing path and a second routing path for said ECBs of said first processor book and routing communication according to the selected path, wherein said first routing path routes communication received at the receptor from the first processor book out to said system rack, and said second routing path re-routes communication received at the receptor from the first processor book back to a selected chip of said first processor book based on a preset wiring scheme designed for technical workload processor books, wherein said wiring means directly connects each of said external routing buses to a destination processor chip that is a largest number of processor hops away from the source processor chip from which said external routing bus originates.   
   
   
       29 . The data processing system of  claim 28 , wherein said logic includes a MUX with a selection mechanism settable by user selection.