Inventor · disambiguated record
Eric Nequist
Also filed as: NEQUIST ERIC · NEQUIST ERIC M · NEQUIST ERIC MARTIN
37 granted patents·1 pending application·414 citations·filing 2003–2024
98Inventor score
Files withCADENCE DESIGN SYSTEMS INC21XCELSIS CORP6NEQUIST ERIC5ADEIA SEMICONDUCTOR INC3BRASHEARS RICHARD VAUGHN1
Top patents by PatentIndex Score
38 records- 0199US11557516B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2020·Granted Jan 17, 2023·7 cites·22 claims
- 0299US10672663B23D chip sharing power circuitXCELSIS CORP·Filed 2018·Granted Jun 2, 2020·25 cites·24 claims
- 0399US10580757B2Face-to-face mounted IC dies with orthogonal top interconnect layersXCELSIS CORP·Filed 2018·Granted Mar 3, 2020·25 cites·20 claims
- 0498US10586786B23D chip sharing clock interconnect layerXCELSIS CORP·Filed 2018·Granted Mar 10, 2020·22 cites·24 claims
- 0597US12142528B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2022·Granted Nov 12, 2024·2 cites·26 claims
- 0691US7725845B1System and method for layout optimization using model-based verificationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 25, 2010·26 cites·20 claims
- 0788US8717182B1Mechanism and method to implement a reader mechanism for a container-based monitor of a consumable productBRASHEARS RICHARD VAUGHN·Filed 2011·Granted May 6, 2014·43 cites·49 claims
- 0888US7861203B2Method and system for model-based routing of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Dec 28, 2010·16 cites·32 claims
- 0988US7461359B1Method and mechanism for determining shape connectivityCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 2, 2008·17 cites·15 claims
- 1088US7096445B1Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 22, 2006·49 cites·31 claims
- 1187US7516433B1Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Apr 7, 2009·15 cites·27 claims
- 1287US2025142942A13d chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 1385US7657860B1Method and system for implementing routing refinement and timing convergenceCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Feb 2, 2010·15 cites·49 claims
- 1484US7665045B1Method and mechanism for identifying and tracking shape connectivityCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Feb 16, 2010·10 cites·29 claims
- 1578US8069426B2Method and mechanism for identifying and tracking shape connectivityNEQUIST ERIC·Filed 2008·Granted Nov 29, 2011·6 cites·21 claims
- 1677US6983440B1Shape abstraction mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jan 3, 2006·23 cites·48 claims
- 1776US8136060B1Method and mechanism for identifying and tracking shape connectivityNEQUIST ERIC·Filed 2009·Granted Mar 13, 2012·5 cites·20 claims
- 1876US7721235B1Method and system for implementing edge optimization on an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 18, 2010·8 cites·28 claims
- 1976US7590955B1Method and system for implementing layout, placement, and routing with merged shapesCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 15, 2009·8 cites·26 claims
- 2076US7100128B1Zone tree method and mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 29, 2006·23 cites·36 claims
- 2176US6981235B1Nearest neighbor mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Dec 27, 2005·23 cites·27 claims
- 2275US8010917B2Method and system for implementing efficient locking to facilitate parallel processing of IC designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Aug 30, 2011·6 cites·12 claims
- 2375US7614028B1Representation, configuration, and reconfiguration of routing method and systemCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 3, 2009·7 cites·57 claims
- 2472US10892252B2Face-to-face mounted IC dies with orthogonal top interconnect layersXCELSIS CORP·Filed 2020·Granted Jan 12, 2021·0 cites·22 claims
- 2570US7698666B2Method and system for model-based design and layout of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Apr 13, 2010·5 cites·22 claims
- 2670US7100129B1Hierarchical gcell method and mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 29, 2006·14 cites·42 claims
- 2769US7904862B2Method and mechanism for performing clearance-based zoningCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 8, 2011·4 cites·27 claims
- 2868US7870517B1Method and mechanism for implementing extraction for an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jan 11, 2011·3 cites·30 claims
- 2966US8631363B2Method and mechanism for identifying and tracking shape connectivityNEQUIST ERIC·Filed 2011·Granted Jan 14, 2014·1 cites·23 claims
- 3066US8375342B1Method and mechanism for implementing extraction for an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2011·Granted Feb 12, 2013·1 cites·24 claims
- 3166US7971173B1Method and system for implementing partial reconfiguration and rip-up of routingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 28, 2011·3 cites·29 claims
- 3265US11157670B2Systems and methods for inter-die block level designXCELSIS CORP·Filed 2020·Granted Oct 26, 2021·0 cites·18 claims
- 3361US8386975B2Method, system, and computer program product for improved electrical analysisCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Feb 26, 2013·2 cites·50 claims
- 3460US10664564B2Systems and methods for inter-die block level designXCELSIS CORP·Filed 2018·Granted May 26, 2020·0 cites·18 claims
- 3550US8316331B1Method and mechanism for implementing extraction for an integrated circuit designNEQUIST ERIC·Filed 2011·Granted Nov 20, 2012·0 cites·24 claims
- 3649US8635574B1Method and mechanism for implementing extraction for an integrated circuit designNEQUIST ERIC·Filed 2011·Granted Jan 21, 2014·0 cites·23 claims
- 3749US8392864B2Method and system for model-based routing of an integrated circuitWHITE DAVID·Filed 2010·Granted Mar 5, 2013·0 cites·22 claims
- 3843US8438512B2Method and system for implementing efficient locking to facilitate parallel processing of IC designsCROSS DAVID·Filed 2011·Granted May 7, 2013·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →