Inventor · disambiguated record
John W. Golz
Also filed as: GOLZ JOHN · GOLZ JOHN W · GOLZ JOHN WALTER
17 granted patents·11 pending applications·251 citations·filing 1998–2024
94Inventor score
Files withIBM28
Top patents by PatentIndex Score
28 records- 0192US9870979B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2015·Granted Jan 16, 2018·10 cites·7 claims
- 0292US9559040B2Double-sided segmented line architecture in 3D integrationIBM·Filed 2013·Granted Jan 31, 2017·14 cites·10 claims
- 0388US6845033B2Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technologyIBM·Filed 2003·Granted Jan 18, 2005·46 cites·8 claims
- 0483US6747890B1Gain cell structure with deep trench capacitorIBM·Filed 2003·Granted Jun 8, 2004·35 cites·10 claims
- 0579US9536809B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2015·Granted Jan 3, 2017·3 cites·3 claims
- 0671US6954387B2Dynamic random access memory with smart refresh schedulerIBM·Filed 2003·Granted Oct 11, 2005·18 cites·20 claims
- 0770US6703312B2Method of forming active devices of different gatelengths using lithographic printed gate images of same lengthIBM·Filed 2002·Granted Mar 9, 2004·16 cites·20 claims
- 0869US9543229B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2013·Granted Jan 10, 2017·2 cites·6 claims
- 0969US6294449B1Self-aligned contact for closely spaced transistorsIBM·Filed 1999·Granted Sep 25, 2001·37 cites·6 claims
- 1068US6429067B1Dual mask process for semiconductor devicesIBM·Filed 2001·Granted Aug 6, 2002·15 cites·10 claims
- 1166US7023758B2Low power manager for standby operation of a memory systemIBM·Filed 2005·Granted Apr 4, 2006·5 cites·20 claims
- 1266US6768143B1Structure and method of making three finger folded field effect transistors having shared junctionsIBM·Filed 2003·Granted Jul 27, 2004·14 cites·20 claims
- 1362US7046572B2Low power manager for standby operation of memory systemIBM·Filed 2003·Granted May 16, 2006·10 cites·9 claims
- 1462US6303275B1Method for resist filling and planarization of high aspect ratio featuresIBM·Filed 2000·Granted Oct 16, 2001·7 cites·20 claims
- 1562US2025365986A1Thermal management structure for memory stacks on logicIBM·Filed 2024·Application pending·0 cites
- 1662US2025343107A1Through-chip vias extending through multiple chips for top-down power redistributionIBM·Filed 2024·Application pending·0 cites
- 1762US2025372476A1Heat spreader with redistribution layerIBM·Filed 2024·Application pending·0 cites
- 1860US2025220926A1High bandwidth memory cubeIBM·Filed 2023·Application pending·0 cites
- 1960US2025201656A1Semiconductor packaging structure with graphite sheetsIBM·Filed 2023·Application pending·0 cites
- 2058US2025022800A1Three-dimensional chip or wafer stackIBM·Filed 2023·Application pending·0 cites
- 2158US2025120101A1Trench moat decoupling capacitorIBM·Filed 2023·Application pending·0 cites
- 2256US2024250070A1Facilitator dies for heterogeneous die stacksIBM·Filed 2023·Application pending·0 cites
- 2355US2024162192A1Stacked 3d cache configuration with on-chip power supportIBM·Filed 2022·Application pending·0 cites
- 2453US2024103065A1Active bridge for chiplet and module inter-communicationIBM·Filed 2022·Application pending·0 cites
- 2553US2023326854A1Power distribution networks for semiconductor chipIBM·Filed 2022·Application pending·0 cites
- 2647US6816397B1Bi-directional read write data structure and method for memoryIBM·Filed 2003·Granted Nov 9, 2004·5 cites·20 claims
- 2746US6472274B1MOSFET with self-aligned channel edge implant and methodIBM·Filed 2000·Granted Oct 29, 2002·4 cites·4 claims
- 2841US6440638B2Method and apparatus for resist planarizationIBM·Filed 1998·Granted Aug 27, 2002·10 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →