Thermal management structure for memory stacks on logic

Abstract

A semiconductor structure that includes a logic die, a plurality of memory die stacks located above the logic die with a plurality of gaps located between the plurality of memory die stacks, and high thermal conductive material located within the plurality of gaps.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a logic die;   a plurality of memory die stacks located above the logic die with a plurality of gaps located between the plurality of memory die stacks; and   a high thermal conductive material located within the plurality of gaps.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 a redistribution layer (RDL) located atop the logic die and between the logic die and the plurality of memory die stacks.   
     
     
         3 . The semiconductor structure of  claim 2 , wherein the RDL includes a dielectric material. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein the RDL includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising:
 a heat spreader located above the plurality of memory die stacks and in contact with the high thermal conductive material located within the plurality of gaps.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein the high thermal conductive material is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the high thermal conductive material within the plurality of gaps surrounds sides of at least one of the plurality of memory die stacks. 
     
     
         8 . A semiconductor structure comprising:
 a logic die including a redistribution layer (RDL);   a plurality of memory die stacks located on the RDL with a plurality of gaps located between the plurality of memory die stacks; and   a high thermal conductive material located within the plurality of gaps.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein the RDL includes a dielectric material. 
     
     
         10 . The semiconductor structure of  claim 8 , wherein the RDL includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal. 
     
     
         11 . The semiconductor structure of  claim 8 , further comprising:
 a heat spreader located above the plurality of memory die stacks and in contact with the high thermal conductive material located within the plurality of gaps.   
     
     
         12 . The semiconductor structure of  claim 8 , wherein the high thermal conductive is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal. 
     
     
         13 . The semiconductor structure of  claim 8 , wherein the high thermal conductive material within the plurality of gaps surrounds sides of at least one of the plurality of memory die stacks. 
     
     
         14 . A method of forming a semiconductor structure, the method comprising:
 providing a logic die prepared with a redistribution layer (RDL);   bonding a plurality of memory die stacks to the RDL; and   providing a high thermal conductive material within a plurality of gaps located between the plurality of memory die stacks, wherein the high thermal conductive material is in contact with the RDL.   
     
     
         15 . The method of  claim 14 , further comprising:
 providing a heat spreader on top of the plurality of memory die stacks and in contact with the high thermal conductive material within the plurality of gaps.   
     
     
         16 . The method of  claim 14 , wherein the providing the plurality of memory die stacks includes:
 providing a plurality of memory wafers;   bonding the plurality of memory wafers; and   after the bonding, etching the plurality of gaps in the plurality of memory wafers to form the plurality of memory die stacks.   
     
     
         17 . The method of  claim 16 , wherein the etching is selected from a group consisting of wet etching, dry etching and a combination of both. 
     
     
         18 . The method of  claim 14 , wherein the RDL includes a dielectric material. 
     
     
         19 . The method of  claim 14 , wherein the RDL includes a material selected from a group consisting of diamond, aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, copper, and a composite of dielectric material and metal. 
     
     
         20 . The method of  claim 14 , wherein the high thermal conductive material located within the plurality of gaps is selected from a group consisting of aluminum nitride, beryllium oxide, beryllium nitride, silicon carbide, graphite, diamond, copper, and a composite of dielectric material and metal.