Inventor · disambiguated record
Douglas W. Kemerer
Also filed as: KEMERER DOUGLAS · KEMERER DOUGLAS W · KEMERER DOUGLAS WAYNE
21 granted patents·2 pending applications·451 citations·filing 1987–2012
96Inventor score
Top patents by PatentIndex Score
23 records- 0195US6577156B2Method and apparatus for initializing an integrated circuit using compressed data from a remote fuseboxIBM·Filed 2000·Granted Jun 10, 2003·106 cites·28 claims
- 0288US6908841B2Support structures for wirebond regions of contact pads over low modulus materialsIBM·Filed 2002·Granted Jun 21, 2005·56 cites·36 claims
- 0387US7397228B2Programmable on-chip sense lineIBM·Filed 2006·Granted Jul 8, 2008·22 cites·11 claims
- 0486US7459958B2Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2006·Granted Dec 2, 2008·14 cites·5 claims
- 0584US5051917AMethod of combining gate array and standard cell circuits on a common semiconductor chipIBM·Filed 1988·Granted Sep 24, 1991·52 cites·7 claims
- 0680US7619398B2Programmable on-chip sense lineIBM·Filed 2008·Granted Nov 17, 2009·4 cites·9 claims
- 0779US7504847B2Mechanism for detection and compensation of NBTI induced threshold degradationIBM·Filed 2006·Granted Mar 17, 2009·12 cites·20 claims
- 0878US7696811B2Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2007·Granted Apr 13, 2010·9 cites·16 claims
- 0974US7849426B2Mechanism for detection and compensation of NBTI induced threshold degradationIBM·Filed 2007·Granted Dec 7, 2010·6 cites·13 claims
- 1074US7076749B2Method and system for improving integrated circuit manufacturing productivityIBM·Filed 2004·Granted Jul 11, 2006·22 cites·20 claims
- 1172US8191030B2Identifying parasitic diode(s) in an integrated circuit physical designKEMERER DOUGLAS W·Filed 2008·Granted May 29, 2012·5 cites·19 claims
- 1270US5737580AWiring design tool improvement for avoiding electromigration by determining optimal wire widthsIBM·Filed 1995·Granted Apr 7, 1998·56 cites·17 claims
- 1365US7941780B2Intersect area based ground rule for semiconductor designIBM·Filed 2008·Granted May 10, 2011·2 cites·25 claims
- 1463US4786613AMethod of combining gate array and standard cell circuits on a common semiconductor chipIBM·Filed 1987·Granted Nov 22, 1988·22 cites·27 claims
- 1561US5369595AMethod of combining gate array and standard cell circuits on a common semiconductor chipIBM·Filed 1991·Granted Nov 29, 1994·24 cites·9 claims
- 1659US7671666B2Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsIBM·Filed 2008·Granted Mar 2, 2010·1 cites·10 claims
- 1759US7146596B2Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring gridIBM·Filed 2003·Granted Dec 5, 2006·10 cites·17 claims
- 1856US6426890B1Shared ground SRAM cellIBM·Filed 2001·Granted Jul 30, 2002·10 cites·20 claims
- 1953US2008246533A1Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applicationsBARROWS COREY KENNETH·Filed 2008·Application pending·0 cites
- 2049US8756554B2Identifying parasitic diode(s) in an integrated circuit physical designKEMERER DOUGLAS W·Filed 2012·Granted Jun 17, 2014·0 cites·19 claims
- 2149US7490303B2Identifying parasitic diode(s) in an integrated circuit physical designIBM·Filed 2006·Granted Feb 10, 2009·0 cites·3 claims
- 2247US6308302B1Semiconductor wiring technique for reducing electromigrationIBM·Filed 1997·Granted Oct 23, 2001·18 cites·4 claims
- 2342US2007176295A1Contact via scheme with staggered viasIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →