Inventor · disambiguated record
Jessica Hui-Chun Tseng
Also filed as: TSENG JESSICA · TSENG JESSICA H · TSENG JESSICA HUI-CHUN
19 granted patents·5 pending applications·24 citations·filing 2007–2022
90Inventor score
Top patents by PatentIndex Score
24 records- 0184US11900116B1Loosely-coupled slice target file dataIBM·Filed 2021·Granted Feb 13, 2024·1 cites·20 claims
- 0283US10007590B2Identifying and tracking frequently accessed registers in a processorIBM·Filed 2016·Granted Jun 26, 2018·4 cites·17 claims
- 0383US9519479B2Techniques for increasing vector processing utilization and efficiency through vector lane predication predictionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 13, 2016·7 cites·12 claims
- 0480US10379869B2Optimize control-flow convergence on SIMD engine using divergence depthIBM·Filed 2018·Granted Aug 13, 2019·2 cites·20 claims
- 0576US9952876B2Optimize control-flow convergence on SIMD engine using divergence depthIBM·Filed 2014·Granted Apr 24, 2018·3 cites·25 claims
- 0674US11163528B2Reformatting matrices to improve computing efficiencyIBM·Filed 2018·Granted Nov 2, 2021·1 cites·14 claims
- 0773US10936320B1Efficient performance of inner loops on a multi-lane processorIBM·Filed 2019·Granted Mar 2, 2021·1 cites·20 claims
- 0872US11294685B2Instruction fusion using dependence analysisIBM·Filed 2019·Granted Apr 5, 2022·1 cites·20 claims
- 0972US10219556B2Actively controlled performance clothingIBM·Filed 2015·Granted Mar 5, 2019·2 cites·5 claims
- 1069US10949202B2Identifying and tracking frequently accessed registers in a processorIBM·Filed 2018·Granted Mar 16, 2021·1 cites·17 claims
- 1167US12461710B2Reformatting matrices to improve computing efficiencyIBM·Filed 2021·Granted Nov 4, 2025·0 cites·11 claims
- 1263US11836493B2Memory access operations for large graph analyticsIBM·Filed 2022·Granted Dec 5, 2023·0 cites·18 claims
- 1362US10936323B2Optimize control-flow convergence on SIMD engine using divergence depthIBM·Filed 2019·Granted Mar 2, 2021·0 cites·17 claims
- 1457US11868275B2Encrypted data processing design including local buffersIBM·Filed 2021·Granted Jan 9, 2024·0 cites·19 claims
- 1557US10956361B2Processor core design optimized for machine learning applicationsIBM·Filed 2018·Granted Mar 23, 2021·0 cites·20 claims
- 1655US2016147536A1Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two ModesIBM·Filed 2014·Application pending·0 cites
- 1754US10956167B2Mechanism for instruction fusion using tagsIBM·Filed 2019·Granted Mar 23, 2021·0 cites·17 claims
- 1853US10983797B2Program instruction schedulingIBM·Filed 2019·Granted Apr 20, 2021·0 cites·17 claims
- 1951US9021482B2Reordering data responses using ordered indicia in a linked listGANESH BRINDA·Filed 2007·Granted Apr 28, 2015·1 cites·3 claims
- 2050US12008150B2Encrypted data processing design including cleartext register filesIBM·Filed 2021·Granted Jun 11, 2024·0 cites·15 claims
- 2150US2014095716A1Maximizing resources in a multi-application processing environementIBM·Filed 2012·Application pending·0 cites
- 2250US2014095718A1Maximizing resources in a multi-application processing environmentIBM·Filed 2012·Application pending·0 cites
- 2348US2016147537A1Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two ModesIBM·Filed 2015·Application pending·0 cites
- 2447US2023097390A1Tightly-coupled slice target file dataIBM·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →