Inventor · disambiguated record
Stuart E. Greer
Also filed as: GREER STUART E
14 granted patents·2 pending applications·1,442 citations·filing 1978–2003
96Inventor score
Top patents by PatentIndex Score
16 records- 0197US6346469B1Semiconductor device and a process for forming the semiconductor deviceMOTOROLA INC·Filed 2000·Granted Feb 12, 2002·212 cites·20 claims
- 0296US5470787ASemiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the sameMOTOROLA INC·Filed 1994·Granted Nov 28, 1995·251 cites·13 claims
- 0395US6713381B2Method of forming semiconductor device including interconnect barrier layersMOTOROLA INC·Filed 2002·Granted Mar 30, 2004·135 cites·13 claims
- 0493US6451681B1Method of forming copper interconnection utilizing aluminum capping filmMOTOROLA INC·Filed 1999·Granted Sep 17, 2002·159 cites·14 claims
- 0593US4202007AMulti-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layersIBM·Filed 1978·Granted May 6, 1980·86 cites·4 claims
- 0692US5468655AMethod for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modulesMOTOROLA INC·Filed 1994·Granted Nov 21, 1995·148 cites·20 claims
- 0790US6689680B2Semiconductor device and method of formationMOTOROLA INC·Filed 2001·Granted Feb 10, 2004·54 cites·7 claims
- 0890US6107180AMethod for forming interconnect bumps on a semiconductor dieMOTOROLA INC·Filed 1998·Granted Aug 22, 2000·164 cites·24 claims
- 0987US5104695AMethod and apparatus for vapor deposition of material onto a substrateIBM·Filed 1989·Granted Apr 14, 1992·54 cites·16 claims
- 1082US4602271APersonalizable masterslice substrate for semiconductor chipsIBM·Filed 1984·Granted Jul 22, 1986·60 cites·3 claims
- 1179US5597737AMethod for testing and burning-in a semiconductor waferMOTOROLA INC·Filed 1995·Granted Jan 28, 1997·55 cites·19 claims
- 1270US4861425ALift-off process for terminal metalsIBM·Filed 1988·Granted Aug 29, 1989·29 cites·19 claims
- 1356US4598470AMethod for providing improved electrical and mechanical connection between I/O pin and transverse via substrateIBM·Filed 1985·Granted Jul 8, 1986·16 cites·10 claims
- 1455US6117759AMethod for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit packageMOTOROLA INC·Filed 1997·Granted Sep 12, 2000·19 cites·41 claims
- 1540US2004094837A1Semiconductor device and method of formationFiled 2003·Application pending·0 cites
- 1627US2002000665A1Semiconductor device conductive bump and interconnect barrierFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →