US2004094837A1PendingUtilityA1

Semiconductor device and method of formation

Priority: Jul 14, 2001Filed: Nov 7, 2003Published: May 20, 2004
Est. expiryJul 14, 2021(expired)· nominal 20-yr term from priority
Inventors:Stuart E. Greer
H10W 74/147H10W 72/9415H10W 72/952H10W 72/934H10W 72/923H10W 72/251H10W 72/242H10W 72/29H10W 72/012H10W 72/019H10W 72/90
40
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Claims

Abstract

In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy ( 414 ) is formed over a semiconductor bond pad ( 128 ), wherein the underbump metallurgy ( 414 ) comprises a chromium, copper, and nickel phased-region ( 404 ), and wherein the presence of nickel in the phased-region ( 404 ) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu 6 Sn 5 copper-tin intermetallics.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device underbump metallurgy comprising a nickel-containing phased region layer.  
     
     
         2 . The semiconductor device underbump metallurgy of  claim 1 , wherein the nickel-containing phased-region layer further comprises copper and chromium.  
     
     
         3 . The semiconductor device underbump metallurgy of  claim 2 , wherein an amount of chromium 50 wt %, an amount of copper is approximately 25 wt %, and an amount of nickel is approximately 25 wt %.  
     
     
         4 . The semiconductor device underbump metallurgy of  claim 1 , wherein the nickel-containing phased-region layer has a thickness in a range of approximately 100-300 nanometers.  
     
     
         5 . The semiconductor device underbump metallurgy of  claim 1  further comprising: 
 an adhesion layer below the nickel-containing phased-region layer; and  
 an oxidation-inhibiting layer over the nickel-containing phased-region layer.  
 
     
     
         6 . The semiconductor device underbump metallurgy of  claim 5 , wherein: 
 the adhesion layer is further characterized chromium-containing layer; and    the oxidation-inhibiting layer is further characterized as a gold layer.    
     
     
         7 . The semiconductor device underbump metallurgy of  claim 6  further comprising: 
 a conductive bump overlying the semiconductor device underbump metallurgy; and  
 a tin intermetallic within the nickel-containing phased-region layer.  
 
     
     
         8 . The semiconductor device underbump metallurgy of  claim 1 , wherein a concentration of an amount of nickel is varied within the nickel-containing phased-region layer.  
     
     
         9 . The semiconductor device underbump metallurgy of  claim 1 , wherein a concentration of an amount of copper is varied within the nickel-containing phased-region layer.  
     
     
         10 . The semiconductor device underbump metallurgy of  claim 1 , wherein a concentration of an amount of copper and a concentration of an amount of nickel are each evenly distributed within the nickel-containing phased-region layer.  
     
     
         11 . A method for forming a semiconductor device underbump metallurgy comprising forming a nickel-containing phased-region layer as a portion of an underbump metallurgy.  
     
     
         12 . The method of  claim 11  wherein the nickel-containing phased-region layer further comprises copper and chromium.  
     
     
         13 . The method of  claim 12 , wherein an amount of chromium is approximately 50 wt %, an amount of copper is approximately 25 wt % and an amount of nickel is approximately 25 wt %.  
     
     
         14 . The method of  claim 12 , wherein the nickel-containing phased-region layer has a thickness in a range of approximately 100-300 nanometers.  
     
     
         15 . The method of  claim 12  further comprising: 
 forming an adhesion layer below the nickel-containing phased region layer; and,  
 forming an oxidation-inhibiting layer over the nickel-containing phased-region layer.  
 
     
     
         16 . The method of  claim 15 , wherein the adhesion layer is further characterized refractory metal containing layer and the oxidation-inhibiting layer is further characterized as a gold layer.  
     
     
         17 . The method of  claim 15  further comprising forming a tin-containing conductive bump overlying the semiconductor device underbump metallurgy, wherein after reflowing the tin-containing conductive bump, tin migrates from the tin-containing conductive bump to the nickel-containing phased-region and forms an intermetallic comprising nickel and tin.  
     
     
         18 . The method of  claim 11 , wherein a concentration of an amount of nickel is varied within the nickel-containing phased region layer.  
     
     
         19 . The method of  claim 11 , wherein a concentration of an amount of copper is varied within the nickel-containing phased region layer.  
     
     
         20 . The method of  claim 11 , wherein a concentration of an amount of copper and a concentration of an amount of nickel are each evenly distributed within the nickel-containing phased region.

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