Inventor · disambiguated record
Suresh Venkatesan
Also filed as: VENKATESAN SURESH
68 granted patents·32 pending applications·2,310 citations·filing 1991–2025
99Inventor score
Files withPOET TECH INC49MOTOROLA INC13GLOBALFOUNDRIES INC8FREESCALE SEMICONDUCTOR INC7RASHED MAHBUB7
Top patents by PatentIndex Score
100 records- 0199US11686906B1Self-aligned structure and method on interposer-based PICPOET TECH INC·Filed 2021·Granted Jun 27, 2023·12 cites·18 claims
- 0299US10530125B1Vertical cavity surface emitting laserPOET TECH INC·Filed 2018·Granted Jan 7, 2020·21 cites·18 claims
- 0399US5554870AIntegrated circuit having both vertical and horizontal devices and process for making the sameMOTOROLA INC·Filed 1995·Granted Sep 10, 1996·468 cites·22 claims
- 0498US6362057B1Method for forming a semiconductor deviceMOTOROLA INC·Filed 1999·Granted Mar 26, 2002·313 cites·24 claims
- 0597US11543588B2Optical dielectric planar waveguide processPOET TECH INC·Filed 2021·Granted Jan 3, 2023·3 cites·20 claims
- 0696US5273921AMethods for fabricating a dual-gated semiconductor-on-insulator field effect transistorPURDUE RESEARCH FOUNDATION·Filed 1991·Granted Dec 28, 1993·127 cites·29 claims
- 0795US11614584B2Loopback waveguidePOET TECH INC·Filed 2021·Granted Mar 28, 2023·2 cites·20 claims
- 0895US6713381B2Method of forming semiconductor device including interconnect barrier layersMOTOROLA INC·Filed 2002·Granted Mar 30, 2004·135 cites·13 claims
- 0995US5736435AProcess for fabricating a fully self-aligned soi mosfetMOTOROLA INC·Filed 1995·Granted Apr 7, 1998·168 cites·12 claims
- 1094US5960270AMethod for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regionsMOTOROLA INC·Filed 1997·Granted Sep 28, 1999·391 cites·43 claims
- 1193US8581348B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted Nov 12, 2013·20 cites·16 claims
- 1293US2025377499A1Optical dielectric planar waveguide processPOET TECH INC·Filed 2025·Application pending·0 cites
- 1392US11444031B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 13, 2022·2 cites·13 claims
- 1492US6444569B2Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 2001·Granted Sep 3, 2002·60 cites·29 claims
- 1591US9355910B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted May 31, 2016·10 cites·7 claims
- 1691US8987128B2Cross-coupling based design using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Mar 24, 2015·22 cites·20 claims
- 1791US8975712B2Densely packed standard cells for integrated circuit products, and methods of making sameGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 10, 2015·14 cites·15 claims
- 1891US8618607B1Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making sameRASHED MAHBUB·Filed 2012·Granted Dec 31, 2013·17 cites·36 claims
- 1991US2025347741A1Structure and method for testing of pic with an upturned mirrorPOET TECH INC·Filed 2025·Application pending·0 cites
- 2090US5349228ADual-gated semiconductor-on-insulator field effect transistorPURDUE RESEARCH FOUNDATION·Filed 1993·Granted Sep 20, 1994·74 cites·12 claims
- 2190US2025012972A1Optical dielectric waveguide subassembly structuresPOET TECH INC·Filed 2024·Application pending·0 cites
- 2290US2025102733A1Loopback waveguidePOET TECH INC·Filed 2024·Application pending·0 cites
- 2389US9196548B2Methods of using a trench salicide routing layerRASHED MAHBUB·Filed 2012·Granted Nov 24, 2015·11 cites·18 claims
- 2489US6326301B1Method for forming a dual inlaid copper interconnect structureMOTOROLA INC·Filed 1999·Granted Dec 4, 2001·83 cites·16 claims
- 2588US10663660B2Optical dielectric waveguide subassembly structuresPOET TECH INC·Filed 2018·Granted May 26, 2020·4 cites·20 claims
- 2688US2025020716A1Structure and method for testing of pic with an upturned mirrorPOET TECH INC·Filed 2024·Application pending·0 cites
- 2788US2025038111A1Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 2888US2025389911A1Self-aligned structure and method on interposer-based picPOET TECH INC·Filed 2025·Application pending·0 cites
- 2988US2025327983A1Self-aligned structure and method on interposer-based picPOET TECH INC·Filed 2025·Application pending·0 cites
- 3087US9006100B2Middle-of-the-line constructs using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Apr 14, 2015·9 cites·14 claims
- 3187US5627097AMethod for making CMOS device having reduced parasitic capacitanceMOTOROLA INC·Filed 1995·Granted May 6, 1997·72 cites·13 claims
- 3286US12399321B2Optical dielectric planar waveguide processPOET TECH INC·Filed 2024·Granted Aug 26, 2025·0 cites·20 claims
- 3386US12366603B1Structure and method for testing of PIC with an upturned mirrorPOET TECH INC·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 3486US11670908B2Planar laser structure with vertical signal transitionPOET TECH INC·Filed 2020·Granted Jun 6, 2023·1 cites·20 claims
- 3586US10795079B2Methods for optical dielectric waveguide subassembly structurePOET TECH INC·Filed 2018·Granted Oct 6, 2020·3 cites·11 claims
- 3686US2025138260A1Self-aligned buried hetero structure laser structures and interposerPOET TECH INC·Filed 2024·Application pending·0 cites
- 3785US10833018B2Semiconductor device with transistor local interconnectsGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 3885US6274478B1Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 1999·Granted Aug 14, 2001·70 cites·9 claims
- 3985US5459096AProcess for fabricating a semiconductor device using dual planarization layersMOTOROLA INC·Filed 1994·Granted Oct 17, 1995·87 cites·10 claims
- 4085US2025012983A1Self-Aligned Structure and Method on Interposer-based PICPOET TECH INC·Filed 2024·Application pending·0 cites
- 4185US2025164712A1Self-aligned structure and method on interposer-based picPOET TECH INC·Filed 2024·Application pending·0 cites
- 4284US12174421B2Loopback waveguidePOET TECH INC·Filed 2023·Granted Dec 24, 2024·0 cites·20 claims
- 4384US12164148B2Loopback waveguidePOET TECH INC·Filed 2023·Granted Dec 10, 2024·0 cites·20 claims
- 4484US8621074B2Intelligent work load managerSHIKARI FAIYAZ·Filed 2012·Granted Dec 31, 2013·9 cites·13 claims
- 4584US2024345340A1Self-aligned structure and method on interposer-based picPOET TECH INC·Filed 2024·Application pending·0 cites
- 4683US7456055B2Process for forming an electronic device including semiconductor finsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 25, 2008·10 cites·19 claims
- 4782US12222566B2Self-aligned structure and method on interposer-based PICPOET TECH INC·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 4882US12099236B2Optical dielectric waveguide subassembly structuresPOET TECH INC·Filed 2022·Granted Sep 24, 2024·0 cites·20 claims
- 4982US6551919B2Method for forming a dual inlaid copper interconnect structureMOTOROLA INC·Filed 2001·Granted Apr 22, 2003·23 cites·6 claims
- 5081US12007604B2Optical dielectric planar waveguide processPOET TECH INC·Filed 2023·Granted Jun 11, 2024·0 cites·20 claims
Showing the top 50 of 100 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Suresh Venkatesan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →