Inventor · disambiguated record
Larry Edward Thatcher
Also filed as: THATCHER LARRY · THATCHER LARRY E · THATCHER LARRY EDWARD
28 granted patents·2 pending applications·887 citations·filing 1989–2008
97Inventor score
Top patents by PatentIndex Score
30 records- 0184US6021485AForwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matchingIBM·Filed 1997·Granted Feb 1, 2000·113 cites·24 claims
- 0280US6463511B2System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory modelINTEL CORP·Filed 2000·Granted Oct 8, 2002·27 cites·30 claims
- 0379US6678807B2System and method for multiple store buffer forwarding in a system with a restrictive memory modelINTEL CORP·Filed 2000·Granted Jan 13, 2004·26 cites·20 claims
- 0478US6237081B1Queuing method and apparatus for facilitating the rejection of sequential instructions in a processorIBM·Filed 1998·Granted May 22, 2001·81 cites·20 claims
- 0577US6336183B1System and method for executing store instructionsIBM·Filed 1999·Granted Jan 1, 2002·71 cites·16 claims
- 0675US6611900B2System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory modelINTEL CORP·Filed 2002·Granted Aug 26, 2003·19 cites·20 claims
- 0773US6266768B1System and method for permitting out-of-order execution of load instructionsIBM·Filed 1998·Granted Jul 24, 2001·63 cites·16 claims
- 0871US6543002B1Recovery from hang condition in a microprocessorIBM·Filed 1999·Granted Apr 1, 2003·55 cites·25 claims
- 0969US5931957ASupport for out-of-order execution of loads and stores in a processorIBM·Filed 1997·Granted Aug 3, 1999·57 cites·1 claims
- 1066US6336168B1System and method for merging multiple outstanding load miss instructionsIBM·Filed 1999·Granted Jan 1, 2002·46 cites·19 claims
- 1162US6901540B1TLB parity error recoveryIBM·Filed 1999·Granted May 31, 2005·42 cites·22 claims
- 1262US4961162AMultiprocessing system for performing floating point arithmetic operationsIBM·Filed 1989·Granted Oct 2, 1990·31 cites·12 claims
- 1361US5613080AMultiple execution unit dispatch with instruction shifting between first and second instruction buffers based upon data dependencyIBM·Filed 1996·Granted Mar 18, 1997·39 cites·20 claims
- 1456US6301654B1System and method for permitting out-of-order execution of load and store instructionsIBM·Filed 1998·Granted Oct 9, 2001·34 cites·21 claims
- 1555US6085289AMethod and system for load data formatting and improved method for cache line organizationIBM·Filed 1997·Granted Jul 4, 2000·29 cites·28 claims
- 1652US6477635B1Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasingIBM·Filed 1999·Granted Nov 5, 2002·25 cites·14 claims
- 1751US6338128B1System and method for invalidating an entry in a translation unitIBM·Filed 1999·Granted Jan 8, 2002·24 cites·6 claims
- 1850US8312309B2Technique for promoting determinism among multiple clock domainsHENDRICKSON ERIC L·Filed 2008·Granted Nov 13, 2012·1 cites·20 claims
- 1948US7216274B2Flexible scan architectureINTEL CORP·Filed 2003·Granted May 8, 2007·3 cites·38 claims
- 2046US6298436B1Method and system for performing atomic memory accesses in a processor systemIBM·Filed 1999·Granted Oct 2, 2001·18 cites·11 claims
- 2145US2004019753A1System and method for multiple store buffer forwarding in a system with a restrictive memory modelINTEL CORP·Filed 2003·Application pending·0 cites
- 2244US6289428B1Superscaler processor and method for efficiently recovering from misaligned data addressesIBM·Filed 1999·Granted Sep 11, 2001·16 cites·14 claims
- 2341US6658555B1Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipelineIBM·Filed 1999·Granted Dec 2, 2003·12 cites·17 claims
- 2441US6021467AApparatus and method for processing multiple cache misses to a single cache lineIBM·Filed 1996·Granted Feb 1, 2000·13 cites·16 claims
- 2538US6425069B1Optimization of instruction stream execution that includes a VLIW dispatch groupIBM·Filed 1999·Granted Jul 23, 2002·10 cites·6 claims
- 2637US6079002ADynamic expansion of execution pipeline stagesIBM·Filed 1997·Granted Jun 20, 2000·9 cites·27 claims
- 2737US5506957ASynchronization for out of order floating point data loadsIBM·Filed 1995·Granted Apr 9, 1996·11 cites·17 claims
- 2836US2007168767A1Flexible scan architectureJABER TALAL K·Filed 2006·Application pending·0 cites
- 2934US5974259AData processing system and method of operation having input/output drivers with reduced power consumption and noise levelsIBM·Filed 1996·Granted Oct 26, 1999·8 cites·20 claims
- 3032US6490653B1Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing systemIBM·Filed 1999·Granted Dec 3, 2002·4 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →