System and method for multiple store buffer forwarding in a system with a restrictive memory model

Abstract

The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.

What is claimed is:  
     
         1 . A method for multiple store buffer forwarding in a system with a restrictive memory model, the method comprising: 
 executing a plurality of store instructions;    executing a load instruction;    determining that a memory region addressed by the load instruction matches a cacheline address in a memory;    determining that data stored by the plurality of store instructions completely covers the memory region addressed by the load instruction; and    transmitting a store forward is OK signal.    
     
     
         2 . The method of  claim 1 , wherein executing the plurality of store instructions comprises: 
 performing a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of the memory region addressed by the load instruction.    
     
     
         3 . The method of  claim 2 , wherein executing a load instruction comprises: loading the data from the contiguous memory locations in the memory; and generating the store forward is OK signal.  
     
     
         4 . The method of  claim 3 , wherein loading the data from the contiguous memory locations in the memory begins after performing the plurality of store operations begins, and loading the data from the contiguous memory locations in the memory completes before the plurality of store operations become globally observed in the system.  
     
     
         5 . The method of  claim 1 , wherein executing the load instruction comprises: 
 loading the data from a write combining buffer; and    generating the store forward is OK signal.    
     
     
         6 . The method of  claim 1 , wherein determining that a memory region addressed by the load instruction matches a cacheline address in a memory comprises: 
 comparing an address of the memory region and the cacheline address; and    determining that the address of the memory region is the same address as the cacheline address.    
     
     
         7 . The method of  claim 1 , wherein determining that the data stored by the plurality of store instructions completely covers the memory region addressed by the load instruction comprises: 
 determining that a size of the data stored by the plurality of store instructions equals a size of the memory region addressed by the load instruction.    
     
     
         8 . The method of  claim 1 , further comprising: 
 terminating, if an address of the memory region and the cacheline address in the memory are different.    
     
     
         9 . The method of  claim 1 , further comprising: 
 re-executing the load instruction, if the memory region is incompletely covered by the data stored by the plurality of store instructions.    
     
     
         10 . The method of  claim 1 , wherein intermediate results from the plurality of store instructions are invisible to other concurrent processes.  
     
     
         11 . The method of  claim 1 , wherein the method operates within the restrictive memory model.  
     
     
         12 . A machine-readable medium having stored thereon a plurality of executable instructions for multiple store buffer forwarding in a system with a restrictive memory model, the plurality of instructions comprising instructions to: 
 execute a plurality of store instructions;    execute a load instruction;    determine that a memory region addressed by the load instruction matches a cacheline address in a memory;    determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction; and    transmit a store forward is OK signal.    
     
     
         13 . The machine-readable medium of  claim 12 , wherein the execute the plurality of store instructions instruction comprises an instruction to: 
 perform a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of a the memory region addressed the load instruction.    
     
     
         14 . The machine-readable medium of  claim 13 , wherein the execute a load instruction instruction comprises instructions to: 
 load the data from the contiguous memory locations in the memory; and    generate the store forward is OK signal.    
     
     
         15 . The machine-readable medium of  claim 14 , wherein the load data from the contiguous memory locations in the memory instruction begins executing after the perform the plurality of store operations instruction begins executing, and the load data from the contiguous memory locations in the memory instruction completes executing before the plurality of store operations become globally observed in the system.  
     
     
         16 . The machine-readable medium of  claim 12 , wherein the execute the load instruction comprises instructions to: 
 load the data from a write combining buffer; and    generate the store forward is OK signal.    
     
     
         17 . The machine-readable medium of  claim 12 , wherein the determine that a memory region addressed by the load instruction matches a cacheline address in a memory instruction comprises instructions to: 
 compare the address of the memory region and the cacheline address; and    determine that the address of the memory region is the same address as the cacheline address.    
     
     
         18 . The machine-readable medium of  claim 12 , wherein the determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction instruction comprises an instruction to: 
 determine that a size of the data stored by the plurality of store instructions equals a size of the memory region addressed by the load instruction.    
     
     
         19 . The machine-readable medium of  claim 12 , further comprising an instruction to: 
 terminate, if an address of the memory region and the cacheline address in the memory are different.    
     
     
         20 . The machine-readable medium of  claim 12 , further comprising an instruction to: 
 re-execute the load instruction, if the memory region is incompletely covered by the data stored by the plurality of store instructions.    
     
     
         21 . The machine-readable medium of  claim 12 , wherein the execute the plurality of store instructions instruction comprises an instruction to: 
 execute the plurality of store instructions to produce intermediate results that are invisible to other concurrent processes.    
     
     
         22 . The machine-readable medium of  claim 12 , wherein the plurality of executable instructions operate within the restrictive memory model.  
     
     
         23 . A processor system, comprising: 
 a processor;    a system memory coupled to the processor; and    a non-volatile memory coupled to the processor in which is stored an article of manufacture including instructions adapted to be executed by the processor, the instructions which, when executed, encode instructions in an instruction set to enable multiple store buffer forwarding in a system with a restrictive memory model, the article of manufacture comprising instructions to: 
 execute a plurality of store instructions;  
 execute a load instruction;  
 determine that a memory region addressed by the load instruction matches a cacheline address in a memory;  
 determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction; and  
 transmit a store forward is OK signal.  
   
     
     
         24 . The processor system of  claim 23 , the processor comprising: 
 a write combining buffer, the write combining buffer including: 
 a comparator, the comparator being configured to receive and compare an incoming load operation target address with all cacheline addresses of existing write combining buffer entries;  
 an address and data buffer coupled to the comparator;  
 a data valid bits buffer coupled to the address and data buffer;  
 a multiplexer coupled to the data valid bits buffer; and  
 a comparison circuit coupled to the multiplexer.  
   
     
     
         25 . The processor system of  claim 24 , the multiplexer being configured to: 
 receive a byte valid vector from the data valid bits buffer;    receive address bits from the load operation and output valid bits;    select a group of valid bits from the byte valid vector; and    output the group of valid bits.    
     
     
         26 . The processor system of  claim 24 , the comparison circuit being configured to: 
 receive the group of valid bits;    receive an incoming load operation byte mask;    determine that it is acceptable to forward the data using the group of valid bits and the incoming load operation byte mask; and    produce a forward OK signal.    
     
     
         27 . The article of manufacture of  claim 23 , wherein the execute the plurality of store instructions instruction comprises an instruction to: 
 perform a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of a the memory region addressed the load instruction.    
     
     
         28 . The machine-readable medium of  claim 27 , wherein the execute a load instruction instruction comprises instructions to: 
 load the data from the contiguous memory locations in the memory; and    generate the store forward is OK signal.    
     
     
         29 . The machine-readable medium of  claim 28 , wherein the load data from the contiguous memory locations in the memory instruction begins executing after the perform the plurality of store operations instruction begins executing, and the load data from the contiguous memory locations in the memory instruction completes executing before the plurality of store operations become globally observed in the system.  
     
     
         30 . The processor system of  claim 23 , wherein said processor is implemented as a multi-processor having associated with each said multi-processor a separate set of hardware resources.