Inventor · disambiguated record
Douglas J. Feist
Also filed as: FEIST DOUGLAS · FEIST DOUGLAS J
4 granted patents·1 pending application·32 citations·filing 2005–2013
71Inventor score
Top patents by PatentIndex Score
5 records- 0186US7202656B1Methods and structure for improved high-speed TDF testing using on-chip PLLLSI LOGIC CORP·Filed 2005·Granted Apr 10, 2007·19 cites·4 claims
- 0276US7081841B1Analog to digital converter built in self testLSI LOGIC CORP·Filed 2005·Granted Jul 25, 2006·11 cites·3 claims
- 0351US7240264B2Scan test expansion moduleLSI CORP·Filed 2005·Granted Jul 3, 2007·2 cites·3 claims
- 0446US2014070849A1Methods and structure for on-chip clock jitter testing and analysisLSI CORP·Filed 2013·Application pending·0 cites
- 0534US8619935B2Methods and structure for on-chip clock jitter testing and analysisFEIST DOUGLAS J·Filed 2010·Granted Dec 31, 2013·0 cites·12 claims
Join the waitlist — get patent alerts
Get an alert when Douglas J. Feist files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →