Methods and structure for on-chip clock jitter testing and analysis

Abstract

Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed

What is claimed is: 
     
         1 . A circuit within an integrated circuit (IC) for testing jitter of an application clock signal generated within the IC, the circuit comprising:
 a sample clock generator coupled to receive an external reference clock signal and adapted to generate a sample clock signal based on the reference clock signal wherein the reference clock signal is used within the IC to generate the application clock signal and wherein the sample clock signal is generated by adding an incremental delay duration to each of a plurality of pulses of the reference clock signal received by the sample clock generator;   an edge-triggered flip-flop coupled to receive the application clock signal and coupled to receive the sample clock signal wherein the flip-flop is adapted to latch the present value of the application clock signal responsive to each rising edge of the sample clock signal and is further adapted to output the present latched value;   a counter coupled to receive the sample clock signal and coupled to receive the present latched value wherein the counter is adapted to increment a count value responsive detecting a logic high on the present latched value at a rising edge of the sample clock signal and is adapted to output its present count value; and   a comparator coupled to receive the present count value and coupled to receive the sample clock signal wherein the comparator is adapted to compare the present count value to an acceptable limits range at a rising edge of the sample clock signal and is adapted to output a pass/fail signal indicating whether the present count value is within the acceptable limits range or is outside the acceptable limits range.   
     
     
         2 . The circuit of  claim 1  further comprising:
 a limits range memory adapted to store a plurality of acceptable limits ranges, each range associated with a corresponding present latched value, the limits range memory further adapted to apply the acceptable limits range corresponding to a present latched value to the comparator circuit, wherein the limits range memory is further adapted to receive the acceptable limits ranges from an external source. 
 
     
     
         3 . The circuit of  claim 2  further comprising:
 a count data memory adapted to store the present count value corresponding to each present latched value and further adapted to apply the present count value corresponding to the present latched value to the comparator circuit. 
 
     
     
         4 . The circuit of  claim 1 , wherein:
 the sample clock generator further comprises:   a programmable delay line coupled to receive the reference clock signal and adapted add a presently programmed delay to the reference clock signal to generate the sample clock signal; and   control logic coupled to receive the reference clock signal and coupled with the programmable delay line wherein the control logic is adapted to re-program the presently programmed delay in response to each of a plurality of rising edges of the reference clock signal wherein each re-programming of the programmable delay line adds an incremental delay amount to the programmable delay line.   
     
     
         5 . The circuit of  claim 1 , wherein:
 the edge-triggered flip-flop is further adapted to apply the present latched value as an output of the flip-flop via an electrical pathway to the counter.   
     
     
         6 . The circuit of  claim 1 , wherein:
 the comparator is further adapted to compare the present count value to an acceptable limits range presently applied to an input path of the comparator.   
     
     
         7 . The circuit of  claim 1 , wherein:
 the acceptable limits range comprises a maximum acceptable limits value; and   the comparator further comprises a maximum value comparator circuit adapted to compare the present count value to a maximum acceptable limits value to determine if the present cumulative count value exceeds the corresponding maximum acceptable value.   
     
     
         8 . The circuit of  claim 7 , wherein:
 the maximum value comparator circuit is further adapted to read the maximum acceptable limits value from an input of the maximum value comparator circuit.   
     
     
         9 . The circuit of  claim 1 , wherein:
 the acceptable limits range comprises a minimum acceptable limits value; and   the comparator further comprises a minimum value comparator circuit adapted to compare the present count value to a minimum acceptable limits value to determine if the present cumulative count value is below the corresponding minimum acceptable value.   
     
     
         10 . The circuit of  claim 9 , wherein:
 the minimum value comparator circuit is further adapted to read the minimum acceptable limits value from an input of the minimum value comparator circuit.   
     
     
         11 . A method, operable within a circuit of an integrated circuit (IC), for testing and analyzing jitter of a Phase Locked Loop (PLL) generated application clock signal within the IC, the method comprising:
 receiving, at a sample clock generator, an external reference clock signal;   generating, at the sample clock generator, a sample clock signal based on the reference clock signal wherein the reference clock signal is used within the IC to generate the application clock signal and wherein the sample clock signal is generated by adding an incremental delay duration to each of a plurality of pulses of the reference clock signal received by the sample clock generator;   receiving, at an edge-triggered flip-flop, the application clock signal and the sample clock signal;   latching, at the edge-triggered flip-flop, the present value of the application clock signal responsive to each rising edge of the sample clock signal;   applying the sample clock signal and the present latched value to a counter;   incrementing, at the counter, a count value responsive detecting a logic high on the present latched value at a rising edge of the sample clock signal;   applying the sample clock signal and the present latched value to a comparator;   comparing, at the comparator, the present count value to an acceptable limits range at a rising edge of the sample clock signal; and   applying, via the comparator, a pass/fail signal indicating whether the present count value is within the acceptable limits range or is outside the acceptable limits range.   
     
     
         12 . The method of  claim 11  further comprising:
 storing a plurality of acceptable limits ranges in a limits range memory, each range associated with a corresponding present latched value; and 
 applying, via the limits range memory, the acceptable limits range corresponding to a present latched value to the comparator. 
 
     
     
         13 . The method of  claim 12  further comprising:
 storing, within a count data memory, a present count value corresponding to each present latched value. 
 
     
     
         14 . The method of  claim 11 , further comprising:
 receiving, at a programmable delay line of the sample clock generator, the reference clock signal;   adding a presently programmed delay to the reference clock signal to generate the sample clock signal; and   re-programming, at the sample clock generator, the presently programmed delay in response to each of a plurality of rising edges of the reference clock signal wherein each re-programming of the programmable delay line adds an incremental delay amount to the programmable delay line.   
     
     
         15 . The method of  claim 11 , further comprising:
 applying the present latched value as an output of the flip-flop via an electrical pathway to the counter.   
     
     
         16 . The method of  claim 11 , further comprising:
 comparing, at the comparator, the present count value to an acceptable limits range presently applied to an input path of the comparator.   
     
     
         17 . The method of  claim 11 , wherein:
 the acceptable limits range comprises a maximum acceptable limits value, and the method further comprises:   comparing the present count value to a maximum acceptable limits value to determine if the present cumulative count value exceeds the corresponding maximum acceptable value.   
     
     
         18 . The method of  claim 17 , further comprising:
 reading the maximum acceptable limits value from an input of the comparator.   
     
     
         19 . The method of  claim 11 , wherein:
 the acceptable limits range comprises a minimum acceptable limits value, and the method further comprises:   comparing the present count value to a minimum acceptable limits value to determine if the present cumulative count value is below the corresponding minimum acceptable value.   
     
     
         20 . The method of  claim 19 , further comprising:
 reading the minimum acceptable limits value from an input of the comparator.