Inventor · disambiguated record
Gauri Karve
Also filed as: KARVE GAURI · KARVE GAURI V
79 granted patents·6 pending applications·198 citations·filing 2007–2023
98Inventor score
Top patents by PatentIndex Score
85 records- 0198US9721848B1Cutting fins and gates in CMOS devicesIBM·Filed 2016·Granted Aug 1, 2017·32 cites·20 claims
- 0295US9917196B1Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2016·Granted Mar 13, 2018·8 cites·8 claims
- 0394US10381437B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2017·Granted Aug 13, 2019·6 cites·11 claims
- 0494US9287264B1Epitaxially grown silicon germanium channel FinFET with silicon underlayerGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 15, 2016·15 cites·12 claims
- 0593US11239316B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Feb 1, 2022·4 cites·20 claims
- 0692US11127815B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Sep 21, 2021·4 cites·20 claims
- 0792US9881937B2Preventing strained fin relaxationIBM·Filed 2017·Granted Jan 30, 2018·6 cites·10 claims
- 0892US9331148B1FinFET device with channel strainIBM·Filed 2015·Granted May 3, 2016·6 cites·9 claims
- 0991US9640640B1FinFET device with channel strainIBM·Filed 2016·Granted May 2, 2017·5 cites·9 claims
- 1091US9496371B1Channel protection during fin fabricationIBM·Filed 2015·Granted Nov 15, 2016·7 cites·20 claims
- 1189US10833190B2Super long channel device within VFET architectureIBM·Filed 2019·Granted Nov 10, 2020·4 cites·15 claims
- 1289US10734523B2Nanosheet substrate to source/drain isolationIBM·Filed 2018·Granted Aug 4, 2020·6 cites·20 claims
- 1389US9576979B2Preventing strained fin relaxation by sealing fin endsIBM·Filed 2015·Granted Feb 21, 2017·5 cites·9 claims
- 1487US11615992B2Substrate isolated VTFET devicesIBM·Filed 2020·Granted Mar 28, 2023·2 cites·14 claims
- 1587US10615278B2Preventing strained fin relaxationIBM·Filed 2017·Granted Apr 7, 2020·4 cites·3 claims
- 1687US9502411B1Strained finFET device fabricationIBM·Filed 2015·Granted Nov 22, 2016·3 cites·7 claims
- 1787US7445981B1Method for forming a dual metal gate structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 4, 2008·15 cites·20 claims
- 1886US11462631B2Sublithography gate cut physical unclonable functionIBM·Filed 2020·Granted Oct 4, 2022·2 cites·20 claims
- 1986US8017469B2Dual high-k oxides with sige channelFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Sep 13, 2011·14 cites·25 claims
- 2084US9711507B1Separate N and P fin etching for reduced CMOS device leakageIBM·Filed 2016·Granted Jul 18, 2017·3 cites·14 claims
- 2183US10727273B2Magnetoresistive random access memory thin film transistor unit cellIBM·Filed 2018·Granted Jul 28, 2020·2 cites·20 claims
- 2281US9741856B2Stress retention in fins of fin field-effect transistorsIBM·Filed 2015·Granted Aug 22, 2017·2 cites·15 claims
- 2380US10062714B2FinFET device having a high germanium content fin structure and method of making sameIBM·Filed 2016·Granted Aug 28, 2018·2 cites·5 claims
- 2480US9997369B2Margin for fin cut using self-aligned triple patterningIBM·Filed 2016·Granted Jun 12, 2018·2 cites·20 claims
- 2580US9431514B2FinFET device having a high germanium content fin structure and method of making sameST MICROELECTRONICS INC·Filed 2014·Granted Aug 30, 2016·3 cites·21 claims
- 2679US11869937B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2022·Granted Jan 9, 2024·0 cites·17 claims
- 2778US8460996B2Semiconductor devices with different dielectric thicknessesKARVE GAURI V·Filed 2007·Granted Jun 11, 2013·7 cites·15 claims
- 2878US7709331B2Dual gate oxide device integrationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 4, 2010·7 cites·20 claims
- 2977US11869936B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2021·Granted Jan 9, 2024·0 cites·16 claims
- 3076USRE50174EStructure and process to tuck fin tips self-aligned to gatesTESSERA LLC·Filed 2022·Granted Oct 15, 2024·0 cites·24 claims
- 3175US7749829B2Step height reduction between SOI and EPI for DSO and BOS integrationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jul 6, 2010·7 cites·22 claims
- 3271US7790528B2Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 7, 2010·5 cites·21 claims
- 3370US9735275B2Channel replacement and bimodal doping scheme for bulk finFET threshold voltage modulation with reduced performance penaltyIBM·Filed 2015·Granted Aug 15, 2017·1 cites·16 claims
- 3469US10424663B2Super long channel device within VFET architectureIBM·Filed 2017·Granted Sep 24, 2019·1 cites·9 claims
- 3569US10170477B2Forming MOSFET structures with work function modificationIBM·Filed 2015·Granted Jan 1, 2019·1 cites·13 claims
- 3669USRE45955EDual high-K oxides with SiGe channelLUO TIEN YING·Filed 2014·Granted Mar 29, 2016·3 cites·25 claims
- 3769US7666730B2Method for forming a dual metal gate structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Feb 23, 2010·4 cites·20 claims
- 3863US12086528B2Secure fingerprinting of a trusted photomaskIBM·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 3963US10964812B2Integration of input/output device in vertical field-effect transistor technologyIBM·Filed 2019·Granted Mar 30, 2021·0 cites·20 claims
- 4063US10840373B2Integration of input/output device in vertical field-effect transistor technologyIBM·Filed 2019·Granted Nov 17, 2020·0 cites·20 claims
- 4160US10622250B2Dielectric gap fill evaluation for integrated circuitsIBM·Filed 2019·Granted Apr 14, 2020·0 cites·20 claims
- 4260US10121853B2Structure and process to tuck fin tips self-aligned to gatesIBM·Filed 2017·Granted Nov 6, 2018·0 cites·17 claims
- 4360US10121852B2Structure and process to tuck fin tips self-aligned to gatesIBM·Filed 2017·Granted Nov 6, 2018·0 cites·15 claims
- 4459US11673766B2Elevator analytics facilitating passenger destination prediction and resource optimizationIBM·Filed 2018·Granted Jun 13, 2023·0 cites·20 claims
- 4559US11182722B2Cognitive system for automatic risk assessment, solution identification, and action enablementIBM·Filed 2019·Granted Nov 23, 2021·0 cites·20 claims
- 4659US10937810B2Sub-fin removal for SOI like isolation with uniform active fin heightIBM·Filed 2019·Granted Mar 2, 2021·0 cites·20 claims
- 4759US10615276B2Integration of input/output device in vertical field-effect transistor technologyIBM·Filed 2017·Granted Apr 7, 2020·0 cites·15 claims
- 4859US10304689B2Margin for fin cut using self-aligned triple patterningIBM·Filed 2018·Granted May 28, 2019·0 cites·20 claims
- 4959US10211321B2Stress retention in fins of fin field-effect transistorsIBM·Filed 2017·Granted Feb 19, 2019·0 cites·6 claims
- 5059US10211319B2Stress retention in fins of fin field-effect transistorsIBM·Filed 2017·Granted Feb 19, 2019·0 cites·6 claims
Showing the top 50 of 85 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →