Inventor · disambiguated record
Ulrich Krauch
Also filed as: KRAUCH ULRICH
14 granted patents·4 pending applications·63 citations·filing 1997–2018
89Inventor score
Top patents by PatentIndex Score
18 records- 0186US9058456B2Method and system to fix early mode slacks in a circuit designIBM·Filed 2013·Granted Jun 16, 2015·11 cites·14 claims
- 0273US6668341B1Storage cell with integrated soft error detection and correctionIBM·Filed 2000·Granted Dec 23, 2003·22 cites·12 claims
- 0367US9506986B2Integrated circuit chip and a method for testing the sameIBM·Filed 2014·Granted Nov 29, 2016·1 cites·16 claims
- 0464US10317465B2Integrated circuit chip and a method for testing the sameIBM·Filed 2018·Granted Jun 11, 2019·0 cites·4 claims
- 0564US8522182B2Generation of an end point report for a timing simulation of an integrated circuitKRAUCH ULRICH·Filed 2011·Granted Aug 27, 2013·3 cites·20 claims
- 0660US10006965B2Integrated circuit chip and a method for testing the sameIBM·Filed 2016·Granted Jun 26, 2018·0 cites·17 claims
- 0758US10528323B2Circuit for addition of multiple binary numbersIBM·Filed 2018·Granted Jan 7, 2020·0 cites·14 claims
- 0858US7401312B2Automatic method for routing and designing an LSIIBM·Filed 2004·Granted Jul 15, 2008·5 cites·7 claims
- 0956US8612500B2Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematicHALLER WILHELM·Filed 2008·Granted Dec 17, 2013·2 cites·14 claims
- 1054US10168991B2Circuit for addition of multiple binary numbersIBM·Filed 2016·Granted Jan 1, 2019·0 cites·18 claims
- 1151US2008301616A1Layout Generator for Routing and Designing an LSIIBM·Filed 2008·Application pending·0 cites
- 1244US2008071852A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 1344US2009112963A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 1443US9996656B2Detecting dispensable inverter chains in a circuit designIBM·Filed 2016·Granted Jun 12, 2018·0 cites·20 claims
- 1540US5928319ACombined binary/decimal adder unitIBM·Filed 1997·Granted Jul 27, 1999·13 cites·12 claims
- 1636US2013227250A1Simd accelerator for data comparisonHALLER WILHELM·Filed 2012·Application pending·0 cites
- 1733US9595304B1Current-mode sense amplifierIBM·Filed 2015·Granted Mar 14, 2017·0 cites·15 claims
- 1833US5944772ACombined adder and logic unitIBM·Filed 1997·Granted Aug 31, 1999·6 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →