Layout Generator for Routing and Designing an LSI

Abstract

According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

1 . A layout generator for creating a layout of the instances of the books of an LSI, comprising:
 a layout generator which passes the coordinates of a generated pin to a wiring tool and wherein said wiring tool connects the generated pin with the corresponding end of said initial route, and   means for generating a layout for instances to be connected of a circuit design book providing LSI switching elements and logic units based on which a circuit design can be generated by considering predefined pin locations, especially pin locations determined by said wiring tool.   
   
   
       2 . The layout generator according to  claim 1  further including means for generating an initial route between two areas defined according to measurements of the size of said two areas of said two instances to be connected, wherein the initial route is optimized according to given design rules; and means for determining an optimized pin location for said instances.