Inventor · disambiguated record
Suresh Chittor
Also filed as: CHITTOR SURESH · CHITTOR SURESH S
18 granted patents·3 pending applications·437 citations·filing 1994–2024
95Inventor score
Top patents by PatentIndex Score
21 records- 0196US7644347B2Silent data corruption mitigation using error correction code with embedded signaling fault detectionINTEL CORP·Filed 2005·Granted Jan 5, 2010·84 cites·19 claims
- 0292US7734980B2Mitigating silent data corruption in a buffered memory module architectureINTEL CORP·Filed 2005·Granted Jun 8, 2010·30 cites·27 claims
- 0383US11250902B2Method and apparatus to reduce power consumption for refresh of memory devices on a memory moduleINTEL CORP·Filed 2019·Granted Feb 15, 2022·2 cites·17 claims
- 0483US5592610AMethod and apparatus for enhancing the fault-tolerance of a networkINTEL CORP·Filed 1994·Granted Jan 7, 1997·130 cites·24 claims
- 0581US12405904B2Sharing memory and I/O services between nodesINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 0681US7991875B2Link level retry schemeINTEL CORP·Filed 2006·Granted Aug 2, 2011·10 cites·21 claims
- 0780US10915468B2Sharing memory and I/O services between nodesINTEL CORP·Filed 2013·Granted Feb 9, 2021·4 cites·25 claims
- 0877US7016304B2Link level retry schemeINTEL CORP·Filed 2001·Granted Mar 21, 2006·25 cites·17 claims
- 0977US6298420B1Coherent variable length reads from system memoryINTEL CORP·Filed 2000·Granted Oct 2, 2001·23 cites·2 claims
- 1069US2022012189A1Sharing memory and i/o services between nodesINTEL CORP·Filed 2021·Application pending·0 cites
- 1166US2019065415A1Technologies for local disaggregation of memoryINTEL CORP·Filed 2018·Application pending·0 cites
- 1260US5987552ABus protocol for atomic transactionsINTEL CORP·Filed 1998·Granted Nov 16, 1999·37 cites·28 claims
- 1359US6021457AMethod and an apparatus for minimizing perturbation while monitoring parallel applicationsINTEL CORP·Filed 1997·Granted Feb 1, 2000·40 cites·13 claims
- 1458US7486685B2System for sharing channels by interleaving flitsRANKIN LINDA J·Filed 2001·Granted Feb 3, 2009·6 cites·18 claims
- 1551US11567877B2Memory utilized as both system memory and near memoryINTEL CORP·Filed 2019·Granted Jan 31, 2023·0 cites·19 claims
- 1651US10936507B2System, apparatus and method for application specific address mappingINTEL CORP·Filed 2019·Granted Mar 2, 2021·0 cites·20 claims
- 1749US11216386B2Techniques for setting a 2-level auto-close timer to access a memory deviceINTEL CORP·Filed 2019·Granted Jan 4, 2022·0 cites·21 claims
- 1845US6061764ACoherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactionsINTEL CORP·Filed 1998·Granted May 9, 2000·16 cites·12 claims
- 1942US6195722B1Method and apparatus for deferring transactions on a host bus having a third party agentINTEL CORP·Filed 1998·Granted Feb 27, 2001·16 cites·19 claims
- 2041US6145062ASelective conflict write flushINTEL CORP·Filed 1998·Granted Nov 7, 2000·14 cites·13 claims
- 2137US2007150699A1Firm partitioning in a system with a point-to-point interconnectSCHOINAS IOANNIS T·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →