Sharing memory and i/o services between nodes

Abstract

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

What is claimed is: 
     
         1 . An apparatus comprising:
 a board comprising Peripheral Component Interconnect Express (PCIe) electricals, wherein the PCIe electricals are to implement a PCIe physical layer;   first protocol stack circuitry to implement at least a portion of a PCIe stack, wherein the first protocol stack circuitry is to generate PCIe-based packets and cause the PCIe-based packets to be sent over the PCIe physical layer; and   second protocol stack circuitry to implement at least a portion of another protocol stack, wherein the other protocol stack is to implement a memory interconnect, and the second protocol stack circuity is to generate flits of a different protocol and cause the flits to be sent over the PCIe physical layer.   
     
     
         2 . The apparatus of  claim 1 , wherein the different protocol comprises a non-PCIe protocol. 
     
     
         3 . The apparatus of  claim 1 , further comprising one or more cores. 
     
     
         4 . The apparatus of  claim 1 , wherein the second protocol stack circuity implements two or more of a transaction layer, a protocol layer, and a link layer. 
     
     
         5 . The apparatus of  claim 1 , wherein the other protocol comprises a memory access protocol. 
     
     
         6 . The apparatus of  claim 1 , wherein the other protocol comprises a cache coherent protocol. 
     
     
         7 . The apparatus of  claim 1 , wherein the other protocol realizes a lower latency than PCIe. 
     
     
         8 . The apparatus of  claim 1 , further comprising a controller to multiplex the PCIe-based packets and the flits of the different protocol. 
     
     
         9 . The apparatus of  claim 1 , further comprising a link to connect to another device, wherein the link is implemented by PCIe electricals. 
     
     
         10 . A method comprising:
 generating Peripheral Component Interconnect Express (PCIe)-based packets in a first mode;   sending the PCIe-based packets over PCIe electricals of a board during the first mode, wherein the PCIe electricals implement a PCIe physical layer of a link;   generating flits of a different other protocol in a second mode, wherein the other protocol comprises a memory interconnect protocol; and   sending the flits over the PCIe electricals of a board during the second mode.   
     
     
         11 . The method of  claim 10 , further comprising multiplexing sending of the packets and sending of the flits. 
     
     
         12 . The method of  claim 10 , wherein data sent in the flits has a lower latency than data sent in the packets. 
     
     
         13 . The method of  claim 10 , wherein the packets and flits are sent from a first device on a board to a second device on the board. 
     
     
         14 . The method of  claim 10 , wherein the memory interconnect protocol comprises a cache coherent protocol. 
     
     
         15 . A system comprising:
 an interconnect comprising Peripheral Component Interconnect Express (PCIe) electricals to implement a PCIe physical layer;   a first device;   a second device coupled to the first device via the interconnect, wherein the second device comprises:
 first protocol stack circuitry to implement at least a portion of a PCIe stack, wherein the first protocol stack circuitry is to generate packets of a PCIe-based protocol and cause the packets to be sent over the PCIe physical layer; and 
 second protocol stack circuitry to implement at least a portion of another protocol stack, wherein the other protocol stack is to implement a memory interconnect, and the second protocol stack circuity is to generate flits of a different other protocol and cause the flits to be sent over the PCIe physical layer. 
   
     
     
         16 . The system of  claim 15 , wherein the first device and the second device are on a same package. 
     
     
         17 . The system of  claim 15 , wherein the first device and the second device are on a same board. 
     
     
         18 . The system of  claim 15 , wherein the different protocol comprises a non-PCIe protocol. 
     
     
         19 . The system of  claim 13 , wherein the first device comprises a processor core. 
     
     
         20 . The system of  claim 15 , wherein the second protocol stack circuity implements two or more of a transaction layer, a protocol layer, and a link layer. 
     
     
         21 . The system of  claim 15 , wherein the other protocol comprises a memory access protocol. 
     
     
         22 . The system of  claim 15 , wherein the other protocol allows data communication at a lower latency than the PCIe-based protocol.