Inventor · disambiguated record
Nathaniel R. Chadwick
Also filed as: CHADWICK NATHANIEL R
12 granted patents·1 pending application·34 citations·filing 2007–2019
86Inventor score
Top patents by PatentIndex Score
13 records- 0191US9520876B1Power gating and clock gating in wiring levelsIBM·Filed 2016·Granted Dec 13, 2016·14 cites·19 claims
- 0275US9250645B2Circuit design for balanced logic stressIBM·Filed 2014·Granted Feb 2, 2016·3 cites·12 claims
- 0373US7493229B2Adjusting voltage for a phase locked loop based on temperatureIBM·Filed 2007·Granted Feb 17, 2009·8 cites·13 claims
- 0470US7877222B2Structure for a phase locked loop with adjustable voltage based on temperatureIBM·Filed 2008·Granted Jan 25, 2011·7 cites·19 claims
- 0563US9472269B2Stress balancing of circuitsIBM·Filed 2014·Granted Oct 18, 2016·2 cites·20 claims
- 0655US9383767B2Circuit design for balanced logic stressIBM·Filed 2014·Granted Jul 5, 2016·0 cites·5 claims
- 0753US11422611B2Adaptive frequency optimization in processorsIBM·Filed 2019·Granted Aug 23, 2022·0 cites·20 claims
- 0851US10509457B2Adaptive frequency optimization in processorsIBM·Filed 2017·Granted Dec 17, 2019·0 cites·17 claims
- 0950US9437670B2Light activated test connectionsIBM·Filed 2012·Granted Sep 6, 2016·0 cites·17 claims
- 1050US8943458B1Determining chip burn-in workload using emulated application conditionIBM·Filed 2013·Granted Jan 27, 2015·0 cites·20 claims
- 1148US9099427B2Thermal energy dissipation using backside thermoelectric devicesIBM·Filed 2013·Granted Aug 4, 2015·0 cites·20 claims
- 1242US9575115B2Methodology of grading reliability and performance of chips across waferGLOBALFOUNDRIES INC·Filed 2012·Granted Feb 21, 2017·0 cites·19 claims
- 1341US2015051869A1Method for relating test time and escape rate for multivariate issueIBM·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →