Inventor · disambiguated record
Michael Thomas Vaden
Also filed as: VADEN MICHAEL · VADEN MICHAEL T · VADEN MICHAEL THOMAS
21 granted patents·3 pending applications·401 citations·filing 1995–2022
95Inventor score
Top patents by PatentIndex Score
24 records- 0190US7818550B2Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling systemIBM·Filed 2007·Granted Oct 19, 2010·25 cites·12 claims
- 0287US6832329B2Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failuresIBM·Filed 2001·Granted Dec 14, 2004·53 cites·13 claims
- 0386US7809924B2System for generating effective addressIBM·Filed 2008·Granted Oct 5, 2010·15 cites·5 claims
- 0475US6401192B1Apparatus for software initiated prefetch and method thereforIBM·Filed 1998·Granted Jun 4, 2002·75 cites·8 claims
- 0573US7360058B2System and method for generating effective addressIBM·Filed 2005·Granted Apr 15, 2008·6 cites·3 claims
- 0671US8024647B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2008·Granted Sep 20, 2011·4 cites·22 claims
- 0771US5740399AModified L1/L2 cache inclusion for aggressive prefetchIBM·Filed 1995·Granted Apr 14, 1998·63 cites·5 claims
- 0869US5758119ASystem and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cacheIBM·Filed 1995·Granted May 26, 1998·55 cites·10 claims
- 0960US7376890B2Method and system for checking rotate, shift and sign extension functions using a modulo functionIBM·Filed 2004·Granted May 20, 2008·6 cites·10 claims
- 1060US6760272B2Method and system for supporting multiple cache configurationsIBM·Filed 2000·Granted Jul 6, 2004·6 cites·23 claims
- 1157US6275918B1Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator thresholdIBM·Filed 1999·Granted Aug 14, 2001·32 cites·17 claims
- 1255US12072789B2Resumable instruction generationHUAWEI TECH CO LTD·Filed 2022·Granted Aug 27, 2024·0 cites·20 claims
- 1354US6430680B1Processor and method of prefetching data based upon a detected strideIBM·Filed 1998·Granted Aug 6, 2002·29 cites·16 claims
- 1452US7991816B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2008·Granted Aug 2, 2011·0 cites·10 claims
- 1550US7779234B2System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessorIBM·Filed 2007·Granted Aug 17, 2010·0 cites·18 claims
- 1650US6914849B2Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decodersIBM·Filed 2003·Granted Jul 5, 2005·8 cites·13 claims
- 1747US2006173941A1Systems and methods for implementing logic in a processorBUSABA FADI Y·Filed 2005·Application pending·0 cites
- 1846US8099451B2Systems and methods for implementing logic in a processorBUSABA FADI YUSUF·Filed 2008·Granted Jan 17, 2012·0 cites·20 claims
- 1946US7509365B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2005·Granted Mar 24, 2009·0 cites·1 claims
- 2046US7051179B2Method and system for supporting multiple cache configurationsIBM·Filed 2003·Granted May 23, 2006·0 cites·9 claims
- 2141US6178493B1Multiprocessor stalled store detectionIBM·Filed 1998·Granted Jan 23, 2001·14 cites·17 claims
- 2240US2006179265A1Systems and methods for executing x-form instructionsFLOOD RACHEL M·Filed 2005·Application pending·0 cites
- 2338US5822556ADistributed completion control in a microprocessorIBM·Filed 1997·Granted Oct 13, 1998·10 cites·18 claims
- 2434US2005041518A1Method and system for supporting multiple cache configurationsFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →