Method and system for supporting multiple cache configurations

Abstract

A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

1 - 30 . (Cancelled)  
   
   
       31 . A method of operating a microprocessor for supporting multiple cache configurations, the method comprising: 
 selecting a first cache configuration among the multiple cache configurations during a first boot of the microprocessor; and    communicating the selection of the first cache configuration among the multiple cache configurations during the first boot of the microprocessor to a first memory device and a second memory device.    
   
   
       32 . The method of claims  31 , further comprising: 
 selecting a second cache configuration among the multiple cache configurations during a second boot of the microprocessor; and    communicating the selection of the second cache configuration among the multiple cache configurations during the second boot of the microprocessor to the first memory device and the second memory device.    
   
   
       33 - 35 . (Cancelled)  
   
   
       36 . The method of  claim 32  wherein the first memory device and the second memory device receive the selection of the second cache configuration concurrently.  
   
   
       37 . The method of  claim 32  wherein the selection of the second cache configuration is performed by a configuration register in communication with a multiplexor.  
   
   
       38 . The method of  claim 31  wherein the selection of the first cache configuration is performed by a configuration register in communication with a multiplexor.  
   
   
       39 . The method of  claim 31  wherein the first memory device and the second memory device receive the selection of the first cache configuration concurrently.  
   
   
       40 . A method of selecting a cache configuration, the method comprising: 
 Selecting a first cache configuration among multiple cache configurations during a first boot of a microprocessor;    Sending a control signal indicative of the first cache configuration to a first memory device and a second memory device such that the first memory device and the second memory device receive the control signal concurrently.