Inventor · disambiguated record
Ruggero Castagnetti
Also filed as: CASTAGNETTI RUGGERO
35 granted patents·6 pending applications·684 citations·filing 1997–2013
98Inventor score
Top patents by PatentIndex Score
41 records- 0191US6980462B1Memory cell architecture for reduced routing congestionLSI LOGIC CORP·Filed 2003·Granted Dec 27, 2005·58 cites·36 claims
- 0289US7006370B1Memory cell architectureLSI LOGIC CORP·Filed 2003·Granted Feb 28, 2006·50 cites·30 claims
- 0385US7304874B2Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areasLSI CORP·Filed 2005·Granted Dec 4, 2007·18 cites·16 claims
- 0483US6166403AIntegrated circuit having embedded memory with electromagnetic shieldLSI LOGIC CORP·Filed 1997·Granted Dec 26, 2000·72 cites·14 claims
- 0582US7440356B2Modular design of multiport memory bitcellsLSI CORP·Filed 2006·Granted Oct 21, 2008·13 cites·20 claims
- 0682US6778462B1Metal-programmable single-port SRAM array for dual-port functionalityLSI LOGIC CORP·Filed 2003·Granted Aug 17, 2004·38 cites·20 claims
- 0782US6566171B1Fuse construction for integrated circuit structure having low dielectric constant dielectric materialLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·30 cites·20 claims
- 0882US6472715B1Reduced soft error rate (SER) construction for integrated circuit structuresLSI LOGIC CORP·Filed 2000·Granted Oct 29, 2002·34 cites·13 claims
- 0979US7042747B1Ternary CAM bitcellsLSI LOGIC CORP·Filed 2005·Granted May 9, 2006·13 cites·20 claims
- 1075US8738940B2Power controller for SoC power gating applicationsVENKATRAMAN RAMNATH·Filed 2011·Granted May 27, 2014·5 cites·17 claims
- 1175US8411399B2Defectivity-immune technique of implementing MIM-based decoupling capacitorsVENKATRAMAN RAMNATH·Filed 2010·Granted Apr 2, 2013·4 cites·20 claims
- 1275US6144076AWell formation For CMOS devices integrated circuit structuresLSI LOGIC CORP·Filed 1998·Granted Nov 7, 2000·51 cites·21 claims
- 1375US5953614AProcess for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming stepLSI LOGIC CORP·Filed 1997·Granted Sep 14, 1999·48 cites·23 claims
- 1472US6442061B1Single channel four transistor SRAMLSI LOGIC CORP·Filed 2001·Granted Aug 27, 2002·15 cites·12 claims
- 1571US7082067B2Circuit for verifying the write speed of SRAM cellsLSI LOGIC CORP·Filed 2004·Granted Jul 25, 2006·17 cites·36 claims
- 1671US6806551B2Fuse construction for integrated circuit structure having low dielectric constant dielectric materialLSI LOGIC CORP·Filed 2003·Granted Oct 19, 2004·15 cites·4 claims
- 1770US6664141B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2001·Granted Dec 16, 2003·14 cites·21 claims
- 1869US6566730B1Laser-breakable fuse link with alignment and break point promotion structuresLSI LOGIC CORP·Filed 2000·Granted May 20, 2003·15 cites·28 claims
- 1968US6828653B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2003·Granted Dec 7, 2004·12 cites·6 claims
- 2068US6218276B1Silicide encapsulation of polysilicon gate and interconnectLSI LOGIC CORP·Filed 1997·Granted Apr 17, 2001·28 cites·26 claims
- 2167US8112734B2Optimization with adaptive body biasingMBOUOMBOUO BENJAMIN·Filed 2008·Granted Feb 7, 2012·4 cites·20 claims
- 2267US6413848B1Self-aligned fuse structure and method with dual-thickness dielectricLSI LOGIC CORP·Filed 2000·Granted Jul 2, 2002·14 cites·9 claims
- 2363US6977512B2Method and apparatus for characterizing shared contacts in high-density SRAM cell designLSI LOGIC CORP·Filed 2003·Granted Dec 20, 2005·13 cites·18 claims
- 2462US8589853B2Total power optimization for a logic integrated circuitMBOUOMBOUO BENJAMIN·Filed 2011·Granted Nov 19, 2013·1 cites·8 claims
- 2562US6259146B1Self-aligned fuse structure and method with heat sinkLSI LOGIC CORP·Filed 1998·Granted Jul 10, 2001·26 cites·22 claims
- 2660US6061264ASelf-aligned fuse structure and method with anti-reflective coatingLSI LOGIC CORP·Filed 1998·Granted May 9, 2000·18 cites·16 claims
- 2759US7869251B2SRAM based one-time-programmable memoryLSI CORP·Filed 2008·Granted Jan 11, 2011·4 cites·18 claims
- 2859US6037233AMetal-encapsulated polysilicon gate and interconnectLSI LOGIC CORP·Filed 1998·Granted Mar 14, 2000·18 cites·13 claims
- 2958US6066525AMethod of forming DRAM capacitor by forming separate dielectric layers in a CMOS processLSI LOGIC CORP·Filed 1999·Granted May 23, 2000·15 cites·14 claims
- 3055US6978407B2Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memoryLSI LOGIC CORP·Filed 2003·Granted Dec 20, 2005·4 cites·16 claims
- 3153US6934174B2Reconfigurable memory arraysLSI LOGIC CORP·Filed 2003·Granted Aug 23, 2005·5 cites·26 claims
- 3253US2014040842A1Total power optimization for a logic integrated circuitLSI CORP·Filed 2013·Application pending·0 cites
- 3351US6687114B1High density memory with storage capacitorLSI LOGIC CORP·Filed 2003·Granted Feb 3, 2004·4 cites·8 claims
- 3448US2014028364A1Critical path monitor hardware architecture for closed loop adaptive voltage scaling and method of operation thereofVENKATRAMAN RAMNATH·Filed 2012·Application pending·0 cites
- 3548US2013166931A1Reducing power consumption of memoryCASTAGNETTI RUGGERO·Filed 2011·Application pending·0 cites
- 3643US6770947B2Laser-breakable fuse link with alignment and break point promotion structuresLSI LOGIC CORP·Filed 2003·Granted Aug 3, 2004·1 cites·13 claims
- 3742US6162714AMethod of forming thin polygates for sub quarter micron CMOS processLSI LOGIC CORP·Filed 1997·Granted Dec 19, 2000·7 cites·8 claims
- 3842US2013166930A1Reducing power consumption of memoryZHOU TING·Filed 2011·Application pending·0 cites
- 3941US2014253226A1Power integrity control through active current profile managementLSI CORP·Filed 2013·Application pending·0 cites
- 4037US6586291B1High density memory with storage capacitorLSI LOGIC CORP·Filed 2002·Granted Jul 1, 2003·0 cites·12 claims
- 4133US2014169113A1Enhancing Memory Yield Through Memory Subsystem RepairLSI CORP·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →