Total power optimization for a logic integrated circuit

Abstract

A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement, computing a total power dissipation for the retained logic cells, and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. A method for reducing total power dissipation for logic cell sets and a processor configured to reduce total power dissipation for groups of logic cells are also provided.

What is claimed is: 
     
         1 . A method of reducing total power dissipation for groups of logic cells using Boolean equations, comprising:
 selecting a path;   identifying at least one group of logic cells for analysis in the path;   deriving Boolean equations for the at least one group of logic cells;   listing possible logic cell implementations for each Boolean equation while maintaining original transistor values;   verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement;   computing a total power dissipation for the retained logic cells; and   choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path.   
     
     
         2 . The method as recited in  claim 1  wherein the at least one group of logic cells includes single logic cells or complex logic cells. 
     
     
         3 . The method as recited in  claim 1  wherein the original transistor values correspond to drive strength, threshold voltage or channel length. 
     
     
         4 . The method as recited in  claim 1  wherein the retained logic cells conform to a static timing analysis for the path. 
     
     
         5 . The method as recited in  claim 1  further comprising providing design resources to facilitate reducing total power dissipation. 
     
     
         6 . The method as recited in  claim 5  wherein the design resources are selected from the group consisting of:
 a value change dump; 
 a static timing analysis database; and 
 a logic cell library. 
 
     
     
         7 . A method of reducing total power dissipation for logic cell sets, comprising:
 selecting a path;   choosing a logic cell in the path;   computing a starting total power for the logic cell;   identifying logic cell implementations using different transistor values for logic cell swapping;   verifying path timing for the logic cell implementations to generate timing-verified logic cells that achieve a timing requirement for the path;   comparing an ending total power of the timing-verified logic cells with the starting total power of the logic cell;   choosing one of the timing verified logic cells or the logic cell based on achieving a minimum total power for the path.   
     
     
         8 . The method as recited in  claim 7  wherein the different transistor values include drive strength, threshold voltage or channel length. 
     
     
         9 . The method as recited in  claim 7  wherein the timing requirement is a static timing analysis for the path. 
     
     
         10 . The method as recited in  claim 7  further comprising providing design resources to facilitate reducing total power dissipation. 
     
     
         11 . The method as recited in  claim 10  wherein the design resources are selected from the group consisting of:
 a value change dump; 
 a static timing analysis database; and 
 a logic cell library. 
 
     
     
         12 . A processor configured to reduce total power dissipation for groups of logic cells using Boolean equations, said processor having circuitry configured to:
 select a path;   identify at least one group of logic cells for analysis in the path;   derive Boolean equations for the at least one group of logic cells;   list possible logic cell implementations for each Boolean equation while maintaining original transistor values;   verify path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement;   compute a total power dissipation for the retained logic cells; and   choose a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path.   
     
     
         13 . The processor according to  claim 12 , wherein the at least one group of logic cells includes single logic cells or complex logic cells. 
     
     
         14 . The processor according to  claim 12 , wherein the original transistor values correspond to drive strength, threshold voltage or channel length. 
     
     
         15 . The processor according to  claim 12 , wherein the retained logic cells conform to a static timing analysis for the path. 
     
     
         16 . The processor according to  claim 12 , wherein the circuitry comprises design resources to facilitate reducing total power dissipation. 
     
     
         17 . The processor according to  claim 16 , wherein the design resources are selected from the group consisting of:
 a value change dump;   a static timing analysis database; and   a logic cell library.   
     
     
         18 . A computer program product, comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method of reducing total power dissipation for groups of logic cells using Boolean equations, said method comprising:
 selecting a path;   identifying at least one group of logic cells for analysis in the path;   deriving Boolean equations for the at least one group of logic cells;   listing possible logic cell implementations for each Boolean equation while maintaining original transistor values;   verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement;   computing a total power dissipation for the retained logic cells; and   choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path.   
     
     
         19 . The computer program product according to  claim 18 , wherein said method further comprises providing design resources to facilitate reducing total power dissipation. 
     
     
         20 . The computer program according to  claim 19 , wherein the design resources are selected from the group consisting of:
 a value change dump;   a static timing analysis database; and   a logic cell library.