Inventor · disambiguated record
Ratheesh R. Thankalekshmi
Also filed as: THANKALEKSHMI RATHEESH R · Thankalekshmi Ratheesh Ramachandran
3 granted patents·7 citations·filing 2016–2018
60Inventor score
Files withGLOBALFOUNDRIES INC3
Top patents by PatentIndex Score
3 records- 0178US9530488B1Methods, apparatus and system determining dual port DC contention marginGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 27, 2016·5 cites·20 claims
- 0277US10163914B2Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit failsGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·2 cites·14 claims
- 0358US10332897B2Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit failsGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →