Inventor · disambiguated record
Gill Yong Lee
Also filed as: LEE GILL · LEE GILL Y · LEE GILL YONG · LEE GILL YOUNG
47 granted patents·10 pending applications·2,591 citations·filing 1997–2025
98Inventor score
Files withAPPLIED MATERIALS INC26IBM8INFINEON TECHNOLOGIES AG6SIEMENS AG6INFINEON TECHNOLOGIES CORP3
Top patents by PatentIndex Score
57 records- 0199US7084079B2Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applicationsIBM·Filed 2002·Granted Aug 1, 2006·610 cites·30 claims
- 0299US6531412B2Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applicationsIBM·Filed 2001·Granted Mar 11, 2003·554 cites·9 claims
- 0398US11049695B2Metal contact landing structureMICROMATERIALS LLC·Filed 2020·Granted Jun 29, 2021·8 cites·18 claims
- 0497US11295786B23D dram structure with high mobility channelAPPLIED MATERIALS INC·Filed 2020·Granted Apr 5, 2022·5 cites·8 claims
- 0596US11818877B2Three-dimensional dynamic random access memory (DRAM) and methods of forming the sameAPPLIED MATERIALS INC·Filed 2021·Granted Nov 14, 2023·2 cites·18 claims
- 0696US10790287B2Reducing gate induced drain leakage in DRAM wordlineAPPLIED MATERIALS INC·Filed 2018·Granted Sep 29, 2020·12 cites·10 claims
- 0796US6806096B1Integration scheme for avoiding plasma damage in MRAM technologyINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 19, 2004·175 cites·23 claims
- 0894US10998329B2Methods and apparatus for three dimensional NAND structure fabricationAPPLIED MATERIALS INC·Filed 2019·Granted May 4, 2021·11 cites·9 claims
- 0994US7682841B2Method of forming integrated circuit having a magnetic tunnel junction deviceQIMONDA AG·Filed 2007·Granted Mar 23, 2010·53 cites·48 claims
- 1094US6783999B1Subtractive stud formation for MRAM manufacturingINFINEON TECHNOLOGIES AG·Filed 2003·Granted Aug 31, 2004·71 cites·18 claims
- 1194US6649531B2Process for forming a damascene structureIBM·Filed 2001·Granted Nov 18, 2003·87 cites·20 claims
- 1294US6570256B2Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substratesIBM·Filed 2001·Granted May 27, 2003·85 cites·11 claims
- 1394US6177698B1Formation of controlled trench top isolation layers for vertical transistorsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Jan 23, 2001·144 cites·10 claims
- 1493US11621266B2Method of testing a gap fill for DRAMAPPLIED MATERIALS INC·Filed 2021·Granted Apr 4, 2023·2 cites·11 claims
- 1593US10964717B2Methods and apparatus for three-dimensional NAND structure fabricationAPPLIED MATERIALS INC·Filed 2019·Granted Mar 30, 2021·8 cites·20 claims
- 1692US6103456APrevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabricationSIEMENS AG·Filed 1998·Granted Aug 15, 2000·163 cites·18 claims
- 1791US11552082B2Reducing gate induced drain leakage in DRAM wordlineAPPLIED MATERIALS INC·Filed 2020·Granted Jan 10, 2023·2 cites·10 claims
- 1891US9653311B13D NAND staircase CD fabrication utilizing ruthenium materialAPPLIED MATERIALS INC·Filed 2016·Granted May 16, 2017·12 cites·19 claims
- 1991US6713802B1Magnetic tunnel junction patterning using SiC or SiNINFINEON TECHNOLOGIES AG·Filed 2003·Granted Mar 30, 2004·70 cites·26 claims
- 2089US10529602B1Method and apparatus for substrate fabricationAPPLIED MATERIALS INC·Filed 2018·Granted Jan 7, 2020·5 cites·20 claims
- 2188US7001783B2Mask schemes for patterning magnetic tunnel junctionsIBM·Filed 2004·Granted Feb 21, 2006·58 cites·20 claims
- 2288US6740539B2Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substratesIBM·Filed 2003·Granted May 25, 2004·37 cites·11 claims
- 2388US6607984B1Removable inorganic anti-reflection coating processIBM·Filed 2000·Granted Aug 19, 2003·42 cites·22 claims
- 2486US11171141B2Gap fill methods of forming buried word lines in DRAM without forming bottom voidsAPPLIED MATERIALS INC·Filed 2020·Granted Nov 9, 2021·2 cites·20 claims
- 2585US6060132AHigh density plasma CVD process for making dielectric anti-reflective coatingsSIEMENS AG·Filed 1998·Granted May 9, 2000·79 cites·11 claims
- 2684US6008120ASilicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabricationSIEMENS AG·Filed 1998·Granted Dec 28, 1999·66 cites·16 claims
- 2783US6858441B2MRAM MTJ stack to conductive line alignment methodINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 22, 2005·37 cites·27 claims
- 2881US6849465B2Method of patterning a magnetic memory cell bottom electrode before magnetic stack depositionINFINEON TECHNOLOGIES AG·Filed 2003·Granted Feb 1, 2005·25 cites·23 claims
- 2980US2025351429A1Structure and fabrication method of high voltage mosfet with a vertical drift regionAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
- 3074US12464716B2NAND cell structure with charge trap cutAPPLIED MATERIALS INC·Filed 2022·Granted Nov 4, 2025·0 cites·10 claims
- 3170US6184091B1Formation of controlled trench top isolation layers for vertical transistorsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Feb 6, 2001·32 cites·19 claims
- 3269US12408370B2Structure and fabrication method of high voltage MOSFET with a vertical drift regionAPPLIED MATERIALS INC·Filed 2022·Granted Sep 2, 2025·0 cites·10 claims
- 3369US11545504B2Methods and apparatus for three dimensional NAND structure fabricationAPPLIED MATERIALS INC·Filed 2021·Granted Jan 3, 2023·0 cites·13 claims
- 3469US11430801B2Methods and apparatus for three dimensional NAND structure fabricationAPPLIED MATERIALS INC·Filed 2021·Granted Aug 30, 2022·0 cites·13 claims
- 3568US6300672B1Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabricationSIEMENS AG·Filed 1998·Granted Oct 9, 2001·30 cites·7 claims
- 3666US7368299B2MTJ patterning using free layer wet etching and lift off techniquesINFINEON TECHNOLOGIES AG·Filed 2004·Granted May 6, 2008·10 cites·35 claims
- 3766US7075807B2Magnetic memory with static magnetic offset fieldALTIS SEMICONDUCTOR SNC·Filed 2004·Granted Jul 11, 2006·14 cites·19 claims
- 3866US6020091AHard etch maskSIEMENS AG·Filed 1997·Granted Feb 1, 2000·31 cites·12 claims
- 3964US8178379B2Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuitBLANCHARD PHILIPPE·Filed 2007·Granted May 15, 2012·3 cites·16 claims
- 4063US12482749B2L-type wordline connection structure for three-dimensional memoryAPPLIED MATERIALS INC·Filed 2022·Granted Nov 25, 2025·0 cites·9 claims
- 4163US6281084B1Disposable spacers for improved array gapfill in high density DRAMsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Aug 28, 2001·21 cites·20 claims
- 4262US12477723B2Three dimensional memory device and method of fabricationAPPLIED MATERIALS INC·Filed 2022·Granted Nov 18, 2025·0 cites·11 claims
- 4362US11763856B23-D DRAM structure with vertical bit-lineAPPLIED MATERIALS INC·Filed 2021·Granted Sep 19, 2023·0 cites·18 claims
- 4461US11765889B2Method to scale dram with self aligned bit line processAPPLIED MATERIALS INC·Filed 2022·Granted Sep 19, 2023·0 cites·20 claims
- 4560US12148475B2Selection gate separation for 3D NANDAPPLIED MATERIALS INC·Filed 2022·Granted Nov 19, 2024·0 cites·20 claims
- 4660US11749315B23D DRAM structure with high mobility channelAPPLIED MATERIALS INC·Filed 2021·Granted Sep 5, 2023·0 cites·12 claims
- 4759US5955380AEndpoint detection method and apparatusSIEMENS AG·Filed 1997·Granted Sep 21, 1999·25 cites·12 claims
- 4859US2020202900A13-D DRAM Structure With Vertical Bit-LineAPPLIED MATERIALS INC·Filed 2019·Application pending·0 cites
- 4958US2020235104A1Cap Layer For Bit Line Resistance ReductionAPPLIED MATERIALS INC·Filed 2020·Application pending·0 cites
- 5055US10700072B2Cap layer for bit line resistance reductionAPPLIED MATERIALS INC·Filed 2018·Granted Jun 30, 2020·0 cites·20 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Gill Yong Lee files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →