Inventor · disambiguated record
Bala Haran
Also filed as: HARAN BALA · HARAN BALA S · HARAN BALA SUBRAMANIAN · HARAN BALA SUBRAMANIAN PRANATHARTHI
11 granted patents·5 pending applications·59 citations·filing 2002–2019
86Inventor score
Top patents by PatentIndex Score
16 records- 0192US8673699B2Semiconductor structure having NFET extension last implantsADAM THOMAS N·Filed 2012·Granted Mar 18, 2014·17 cites·11 claims
- 0291US8546203B1Semiconductor structure having NFET extension last implantsCHENG KANGGUO·Filed 2012·Granted Oct 1, 2013·14 cites·23 claims
- 0390US10461173B1Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistorGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 29, 2019·7 cites·19 claims
- 0483US8691687B2Superfilled metal contact vias for semiconductor devicesKELLY JAMES J·Filed 2010·Granted Apr 8, 2014·8 cites·20 claims
- 0574US6753039B2Electrolytic and electroless process for treating metallic surfaces and products formed therebyELISHA HOLDING LLC·Filed 2002·Granted Jun 22, 2004·13 cites·20 claims
- 0659US10658363B2Cut inside replacement metal gate trench to mitigate N-P proximity effectGLOBALFOUNDRIES INC·Filed 2019·Granted May 19, 2020·0 cites·15 claims
- 0754US10446550B2Cut inside replacement metal gate trench to mitigate N-P proximity effectGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 15, 2019·0 cites·17 claims
- 0846US10991689B2Additional spacer for self-aligned contact for only high voltage FinFETsGLOBALFOUNDRIES US INC·Filed 2019·Granted Apr 27, 2021·0 cites·20 claims
- 0945US2004217334A1Electrolytic and electroless process for treating metallic surfaces and products formed therebyFiled 2004·Application pending·0 cites
- 1044US10566328B2Integrated circuit products with gate structures positioned above elevated isolation structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·0 cites·17 claims
- 1144US9269611B2Integrated circuits having gate cap protection and methods of forming the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 23, 2016·0 cites·17 claims
- 1244US2012292706A1Scheme to enable robust integration of band edge devices and alternative channelsEDGE LISA F·Filed 2012·Application pending·0 cites
- 1341US2011303981A1Scheme to Enable Robust Integration of Band Edge Devices and Alternatives ChannelsEDGE LISA F·Filed 2010·Application pending·0 cites
- 1440US10741668B2Short channel and long channel devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 11, 2020·0 cites·18 claims
- 1536US2019096679A1Gate stack processes and structuresGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 1636US2018366553A1Methods of forming an air gap adjacent a gate structure of a finfet device and the resulting devicesGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →