Inventor · disambiguated record
David M. Dobuzinsky
Also filed as: DOBUZINSKY DAVID · DOBUZINSKY DAVID M · DOBUZINSKY DAVID MARK
55 granted patents·7 pending applications·2,627 citations·filing 1991–2013
99Inventor score
Top patents by PatentIndex Score
62 records- 0198US7118986B2STI formation in semiconductor device including SOI and bulk silicon regionsIBM·Filed 2004·Granted Oct 10, 2006·258 cites·26 claims
- 0296US8008713B2Vertical SOI trench SONOS cellIBM·Filed 2009·Granted Aug 30, 2011·37 cites·11 claims
- 0396US5563105APECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming elementIBM·Filed 1994·Granted Oct 8, 1996·332 cites·20 claims
- 0496US5536360AMethod for etching boron nitrideIBM·Filed 1995·Granted Jul 16, 1996·247 cites·4 claims
- 0595US7560360B2Methods for enhancing trench capacitance and trench capacitorIBM·Filed 2006·Granted Jul 14, 2009·34 cites·5 claims
- 0695US5763315AShallow trench isolation with oxide-nitride/oxynitride linerIBM·Filed 1997·Granted Jun 9, 1998·199 cites·9 claims
- 0795US5468687AMethod of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation)IBM·Filed 1994·Granted Nov 21, 1995·129 cites·5 claims
- 0894US7514323B2Vertical SOI trench SONOS cellIBM·Filed 2005·Granted Apr 7, 2009·22 cites·9 claims
- 0994US6570256B2Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substratesIBM·Filed 2001·Granted May 27, 2003·85 cites·11 claims
- 1094US6046487AShallow trench isolation with oxide-nitride/oxynitride linerIBM·Filed 1997·Granted Apr 4, 2000·169 cites·4 claims
- 1192US5330935ALow temperature plasma oxidation processIBM·Filed 1992·Granted Jul 19, 1994·151 cites·10 claims
- 1291US5876788AHigh dielectric TiO2 -SiN composite films for memory applicationsIBM·Filed 1997·Granted Mar 2, 1999·97 cites·31 claims
- 1390US5998100AFabrication process using a multi-layer antireflective layerTOSHIBA KK·Filed 1997·Granted Dec 7, 1999·89 cites·5 claims
- 1488US6740539B2Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substratesIBM·Filed 2003·Granted May 25, 2004·37 cites·11 claims
- 1587US5759746AFabrication process using a thin resistTOSHIBA KK·Filed 1996·Granted Jun 2, 1998·75 cites·17 claims
- 1687US5412246ALow temperature plasma oxidation processIBM·Filed 1994·Granted May 2, 1995·93 cites·8 claims
- 1785US6964897B2SOI trench capacitor cell incorporating a low-leakage floating body array transistorIBM·Filed 2003·Granted Nov 15, 2005·50 cites·25 claims
- 1883US6869542B2Hard mask integrated etch process for patterning of silicon oxide and other dielectric materialsIBM·Filed 2003·Granted Mar 22, 2005·35 cites·17 claims
- 1979US7087532B2Formation of controlled sublithographic structuresIBM·Filed 2004·Granted Aug 8, 2006·22 cites·20 claims
- 2078US5656535AStorage node process for deep trench-based DRAMSIEMENS AG·Filed 1996·Granted Aug 12, 1997·42 cites·20 claims
- 2175US5747866AApplication of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structuresSIEMENS AG·Filed 1997·Granted May 5, 1998·41 cites·13 claims
- 2275US5643823AApplication of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structuresSIEMENS AG·Filed 1995·Granted Jul 1, 1997·45 cites·5 claims
- 2372US7358172B2Poly filled substrate contact on SOI structureIBM·Filed 2006·Granted Apr 15, 2008·4 cites·18 claims
- 2471US7394131B2STI formation in semiconductor device including SOI and bulk silicon regionsIBM·Filed 2006·Granted Jul 1, 2008·4 cites·3 claims
- 2571US6887785B1Etching openings of different depths using a single mask layer method and structureIBM·Filed 2004·Granted May 3, 2005·17 cites·17 claims
- 2671US6518151B1Dual layer hard mask for eDRAM gate etch processIBM·Filed 2001·Granted Feb 11, 2003·14 cites·17 claims
- 2770US6153474AMethod of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrateIBM·Filed 1998·Granted Nov 28, 2000·28 cites·18 claims
- 2869US6093281ABaffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambersIBM·Filed 1998·Granted Jul 25, 2000·19 cites·21 claims
- 2968US7871893B2Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devicesIBM·Filed 2008·Granted Jan 18, 2011·4 cites·13 claims
- 3068US6809027B2Self-aligned borderless contactsIBM·Filed 2002·Granted Oct 26, 2004·12 cites·6 claims
- 3167US5899724AMethod for fabricating a titanium resistorIBM·Filed 1996·Granted May 4, 1999·26 cites·14 claims
- 3265US6960523B2Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM deviceIBM·Filed 2003·Granted Nov 1, 2005·10 cites·15 claims
- 3364US6806177B2Method of making self-aligned borderless contactsIBM·Filed 2003·Granted Oct 19, 2004·10 cites·14 claims
- 3461US8426268B2Embedded DRAM memory cell with additional patterning layer for improved strap formationCHENG KANGGUO·Filed 2010·Granted Apr 23, 2013·1 cites·8 claims
- 3561US8003488B2Shallow trench isolation structure compatible with SOI embedded DRAMIBM·Filed 2007·Granted Aug 23, 2011·2 cites·4 claims
- 3661US6207353B1Resist formulation which minimizes blistering during etchingIBM·Filed 1997·Granted Mar 27, 2001·28 cites·20 claims
- 3759US5622596AHigh density selective SiO2 :Si3 N4 etching using a stoichiometrically altered nitride etch stopIBM·Filed 1995·Granted Apr 22, 1997·23 cites·5 claims
- 3859US5455204AThin capacitor dielectric by rapid thermal processingIBM·Filed 1994·Granted Oct 3, 1995·27 cites·19 claims
- 3958US5204138APlasma enhanced CVD process for fluorinated silicon nitride filmsIBM·Filed 1991·Granted Apr 20, 1993·14 cites·12 claims
- 4057US5217567ASelective etching process for boron nitride filmsIBM·Filed 1992·Granted Jun 8, 1993·25 cites·15 claims
- 4155US6806200B2Method of improving etch uniformity in deep silicon etchingIBM·Filed 2002·Granted Oct 19, 2004·4 cites·8 claims
- 4253US6014310AHigh dielectric TiO2 -SiN composite films for memory applicationsIBM·Filed 1998·Granted Jan 11, 2000·14 cites·8 claims
- 4352US6890815B2Reduced cap layer erosion for borderless contactsIBM·Filed 2003·Granted May 10, 2005·5 cites·25 claims
- 4451US7592245B2Poly filled substrate contact on SOI structureIBM·Filed 2008·Granted Sep 22, 2009·0 cites·9 claims
- 4550US8772850B2Embedded DRAM memory cell with additional patterning layer for improved strap formationIBM·Filed 2013·Granted Jul 8, 2014·0 cites·14 claims
- 4649US2008248625A1Methods for enhancing trench capacitance and trench capacitorCHENG KANGGUO·Filed 2008·Application pending·0 cites
- 4747US5939335AMethod for reducing stress in the metallization of an integrated circuitIBM·Filed 1998·Granted Aug 17, 1999·11 cites·24 claims
- 4846US6208008B1Integrated circuits having reduced stress in metallizationIBM·Filed 1999·Granted Mar 27, 2001·10 cites·11 claims
- 4946US2009047791A1Semiconductor etching methodsIBM·Filed 2007·Application pending·0 cites
- 5046US2009104776A1Methods for forming nested and isolated lines in semiconductor devicesIBM·Filed 2007·Application pending·0 cites
Showing the top 50 of 62 patent records by PatentIndex Score.
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