Methods for enhancing trench capacitance and trench capacitor

Abstract

Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

1 . A method of forming a trench capacitor, the method comprising:
 forming a first portion of a trench;   depositing a dielectric layer in the first portion;   performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall;   depositing a node dielectric; and   filling the trench with a conductor.   
   
   
       2 . The method of  claim 1 , further comprising forming a buried plate in the second portion of the trench. 
   
   
       3 . The method of  claim 1 , wherein the etching in the first stage includes a non-uniform reactive ion etch. 
   
   
       4 . The method of  claim 1 , wherein the dielectric layer includes silicon nitride. 
   
   
       5 . The method of  claim 1 , wherein the etching, including the first stage and the second stage, occurs in a single process chamber. 
   
   
       6 . The method of  claim 1 , wherein the rough sidewall has dimensions of a nanometer scale. 
   
   
       7 . The method of  claim 6 , wherein the rough sidewall has an average amplitude of less than approximately 5 nanometers. 
   
   
       8 . A method comprising:
 forming a trench having a dielectric layer therein; and   first reactive ion etching (RIE) the dielectric layer in the trench to form a micro-mask on a bottom surface of the trench.   
   
   
       9 . The method of  claim 8 , wherein the first RIE forms a spacer on a sidewall of the trench. 
   
   
       10 . The method of  claim 8 , wherein the first RIE is non-uniform. 
   
   
       11 . The method of  claim 8 , further comprising a second reactive ion etching (RIE) to extend the trench into a substrate to form a deep trench below the spacer. 
   
   
       12 . The method of  claim 11 , wherein the second RIE forms the trench with nanometer scale roughness on a trench sidewall. 
   
   
       13 . The method of  claim 12 , wherein the roughness on the trench sidewall has an average amplitude of less than approximately 5 nanometers. 
   
   
       14 . The method of  claim 12 , wherein the first RIE and the second RIE occur in a single process chamber.