Inventor · disambiguated record
Thomas Hans Rinderknecht
Also filed as: RINDERKNECHT THOMAS H · RINDERKNECHT THOMAS HANS
9 granted patents·2 pending applications·256 citations·filing 1999–2010
90Inventor score
Files withRINDERKNECHT THOMAS HANS2CHENG WU-TUNG1HAPKE FRIEDRICH1HILL CHRISTOPHER JOHN1MENTOR GRAPHICS CORP1
Top patents by PatentIndex Score
11 records- 0194US7840865B2Built-in self-test of integrated circuits using selectable weighting of test patternsMENTOR GRAPHICS CORP·Filed 2007·Granted Nov 23, 2010·35 cites·23 claims
- 0293US8726112B2Scan test application through high-speed serial input/outputsRAJSKI JANUSZ·Filed 2009·Granted May 13, 2014·28 cites·44 claims
- 0391US7296249B2Using constrained scan cells to test integrated circuitsRINDERKNECHT THOMAS HANS·Filed 2004·Granted Nov 13, 2007·54 cites·29 claims
- 0490US8280687B2Direct fault diagnostics using per-pattern compactor signaturesCHENG WU-TUNG·Filed 2006·Granted Oct 2, 2012·20 cites·45 claims
- 0577US7644333B2Restartable logic BIST controllerHILL CHRISTOPHER JOHN·Filed 2002·Granted Jan 5, 2010·27 cites·24 claims
- 0674US6295315B1Jitter measurement system and methodFiled 1999·Granted Sep 25, 2001·78 cites·32 claims
- 0765US8448032B2Performance of signature-based diagnosis for logic BISTSHARMA MANISH·Filed 2009·Granted May 21, 2013·4 cites·20 claims
- 0858US6920597B2Uniform testing of tristate nets in logic BISTFiled 2002·Granted Jul 19, 2005·9 cites·31 claims
- 0955US8448008B2High speed clock controlHAPKE FRIEDRICH·Filed 2010·Granted May 21, 2013·1 cites·8 claims
- 1044US2002106014A1Jitter measurement system and methodFiled 2001·Application pending·0 cites
- 1142US2008201670A1Using constrained scan cells to test integrated circuitsRINDERKNECHT THOMAS HANS·Filed 2007·Application pending·0 cites
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