US2002106014A1PendingUtilityA1

Jitter measurement system and method

Priority: Apr 20, 1999Filed: Sep 24, 2001Published: Aug 8, 2002
Est. expiryApr 20, 2019(expired)· nominal 20-yr term from priority
H04L 1/205
44
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Claims

Abstract

A jitter measurement system measures timing variations or “jitter” in a periodic signal waveform as provided, for example, by a phase-locked loop (PLL). In one implementation, the jitter measurement system includes a period gate generator that generates a gate signal with the instantaneous period of output signal waveform F VCO generated by the PLL. The gate signal includes a leading edge and a trailing edge and is delivered to a pair of triggered oscillators that provide respective oscillator output signals with substantially matched frequencies. The oscillators are triggered at the respective leading and trailing edges of the gate signal. The oscillator output signals are delivered to respective oscillation counters and to a coincidence detector. The oscillation counters count the periods of the respective oscillator output signals from when they are triggered until the coincidence detector detects coincidence between the signals (e.g., coincidence between the trailing edges of the signals). A period measurement of the output signal waveform F VCO is determined from the counts obtained by the oscillation counters. Multiple such period measurements are obtained to provide information representing jitter in the output signal waveform F VCO .

Claims

exact text as granted — not AI-modified
1 . A vernier period measurement system for measuring a period in a signal waveform having first and second waveform features, comprising: 
 first and second oscillators that generate respective first and second oscillation signals with substantially matched frequencies, the first and second oscillators being triggered with respect to the respective first and second waveform features;    a coincidence detector that detects when selected portions of the first and second oscillation signals are coincident with each other; and    a counter that provides a measurement count of the periods of at least one of the first and second oscillation signals from when it is triggered to when it is coincident with the other of the first and second oscillation signals.    
     
     
         2 . The system of  claim 1  further comprising a measurement data processor that determines from the count of the periods of the at least one of the first and second oscillation signals a measurement of a time interval between the first and second waveform features.  
     
     
         3 . The system of  claim 1  in which the signal waveform is periodic and plural measurement counts are obtained for the periodic signal waveform and in which the system further comprises a measurement data analysis system for providing a jitter analysis based upon the plural measurement counts.  
     
     
         4 . The system of  claim 3  in which the measurement data analysis system provides a histogram analysis based upon the plural measurement counts.  
     
     
         5 . The system of  claim 1  in which the counter provides a count of the first oscillation signal and the system further comprises a second counter that provides a count of the second oscillation signal.  
     
     
         6 . The system of  claim 1  further comprising a period gate generator that generates a gate signal with representations of the first and second waveform features and the instantaneous period of the signal waveform and in which the first and second oscillators are triggered from the representations of the first and second waveform features, respectively.  
     
     
         7 . The system of  claim 1  in which the signal waveform is periodic and the periodic signal waveform is provided by a phase-locked loop.  
     
     
         8 . The system of  claim 1  in which the signal waveform is periodic and the periodic signal waveform is provided on an integrated circuit and one of more components of the system are included in the integrated circuit as a built-in self test component.  
     
     
         9 . The system of  claim 8  in which all components of the system are included in the integrated circuit as a built-in self test component.  
     
     
         10 . The system of  claim 1  in which the first and second oscillators are maintained in a normally on state and triggering them includes temporarily ending the oscillation signals and then resuming them again with respect to the respective first and second waveform features.  
     
     
         11 . The system of  claim 1  further comprising a single power supply for the first and second oscillators.  
     
     
         12 . The system of  claim 1  in which the first and second waveform features are respective leading and trailing edges of the signal waveform.  
     
     
         13 . A vernier period measurement method for measuring a period in a signal waveform having first and second waveform features, comprising: 
 generating first and second oscillation signals with substantially matched frequencies, the first and second oscillation signals being triggered with respect to the respective first and second waveform features;    detecting when selected portions of the first and second oscillation signals are coincident with each other; and    counting the periods of at least one of the first and second oscillation signals from when it is triggered to when it is coincident with the other of the first and second oscillation signals.    
     
     
         14 . The method of  claim 13  further comprising determining from the count of the periods of the at least one of the first and second oscillation signals a measurement of a time interval between the first and second waveform features.  
     
     
         15 . The method of  claim 13  in which the signal waveform is periodic and the method further comprises obtaining plural counts for the periodic signal waveform and providing a jitter analysis based upon the plural measurement counts.  
     
     
         16 . The method of  claim 15  in which the jitter analysis provides a histogram analysis based upon the plural measurement counts.  
     
     
         17 . The method of  claim 13  further comprising counting the periods of both of the first and second oscillation signals from when they are triggered to when they are coincident with each other.  
     
     
         18 . The method of  claim 13  further comprising generating a gate signal with representations of the first and second waveform features and the instantaneous period of the signal waveform and triggering first and second oscillation signals from the representations of the first and second waveform features, respectively.  
     
     
         19 . The method of  claim 13  in which the signal waveform is periodic and the periodic signal waveform is provided by a phase-locked loop.  
     
     
         20 . The method of  claim 13  in which the signal waveform is periodic and the periodic signal waveform is provided on an integrated circuit and the method is performed by components, one or more of which are included on the integrated circuit as a built-in self test component.  
     
     
         21 . The method of  claim 13  in which the signal waveform is periodic and the periodic signal waveform is provided by a phase-locked loop that is included in an integrated circuit and the method is performed by components, one or more of which are included on the integrated circuit as a built-in self test component.  
     
     
         22 . The method of  claim 13  in which the first and second oscillation signals includes temporarily terminating them and then generating them again with respect to the respective first and second waveform features.  
     
     
         23 . The method of  claim 13  in which the first and second waveform features are respective leading and trailing edges of the signal waveform.  
     
     
         24 . In an integrated circuit that generates a periodic signal waveform having first and second waveform features, a built-in self test component for measuring jitter in periodic signal waveform, comprising: 
 first and second oscillators that generate respective first and second oscillation signals with substantially matched frequencies, the first and second oscillators being triggered with respect to the respective first and second waveform features;    a coincidence detector that detects when selected portions of the first and second oscillation signals are coincident with each other; and    a counter that provides a measurement count of the periods of at least one of the first and second oscillation signals from when it is triggered to when it is coincident with the other of the first and second oscillation signals.    
     
     
         25 . The circuit of  claim 24  further comprising a measurement data processor that determines from the count of the periods of the at least one of the first and second oscillation signals a measurement of a time interval between the first and second waveform features.  
     
     
         26 . The circuit of  claim 24  in which plural measurement counts are obtained for the periodic signal waveform and in which the system further comprises a measurement data analysis system for providing a jitter analysis based upon the plural measurement counts.  
     
     
         27 . The circuit of  claim 26  in which the measurement data analysis system provides a histogram analysis based upon the plural measurement counts.  
     
     
         28 . The circuit of  claim 24  in which the counter provides a count of the first oscillation signal and the system further comprises a second counter that provides a count of the second oscillation signal.  
     
     
         29 . The circuit of  claim 24  further comprising a period gate generator that generates a gate signal with representations of the first and second waveform features and the instantaneous period of the periodic signal waveform and in which the first and second oscillators are triggered from the respective representations of the first and second waveform features, respectively.  
     
     
         30 . The circuit of  claim 24  in which the first and second oscillators are maintained in a normally on state and triggering them includes temporarily ending the oscillation signals and then resuming them again with respect to the respective first and second waveform features.  
     
     
         31 . The circuit of  claim 24  further comprising a single power supply for the first and second oscillators.  
     
     
         32 . The circuit of  claim 24  in which the integrated circuit includes a phase-locked loop that generates the periodic signal waveform.  
     
     
         33 . A jitter measurement system employing two closely matched but not equal oscillators in a vernier measurement scheme where the jitter of the individual oscillators is greater than the jitter measurement resolution.  
     
     
         34 . The method of  claim 33  in which the two oscillators are formed on a common substrate and are coupled to a common voltage supply.

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