Using constrained scan cells to test integrated circuits

Abstract

Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.

1 .- 32 . (canceled) 
     
     
         33 . A circuit, comprising:
 circuit logic;   one or more scan chains coupled to the circuit logic, the one or more scan chains comprising scan cells operable in at least a scan mode and an operational mode; and   test logic coupled to a scan path of at least two of the scan cells, the test logic being configured to load the at least two of the scan cells with either a fixed value or a pseudo-random value while the scan cells are operating in the scan mode.   
     
     
         34 . The circuit of  claim 33 , wherein the test logic is not directly coupled to the circuit logic. 
     
     
         35 . The circuit of  claim 33 , further comprising a pseudo-random pattern generator coupled to the test logic, the pseudo-random pattern generator producing the pseudo-random value. 
     
     
         36 . The circuit of  claim 33 , wherein the pseudo-random pattern generator is a linear feedback shift register (LFSR). 
     
     
         37 . The circuit of  claim 33 , further comprising a phase decoder coupled to the test logic, the phase decoder at least partially producing the fixed value. 
     
     
         38 . The circuit of  claim 37 , further comprising a shift counter having an output signal that is logically coupled with an output signal of the phase decoder, the shift counter being configured to control when the fixed value is loaded by the test logic into the at least two of the scan cells. 
     
     
         39 . The circuit of  claim 38 , wherein the shift counter is configured to load the fixed value during a last shift cycle of the scan mode. 
     
     
         40 . The circuit of  claim 33 , further comprising an observation point in the circuit logic, the observation point having a value indicative of the presence of a fault whose value does not otherwise propagate to circuit logic outputs. 
     
     
         41 . One or more computer-readable media storing computer-executable instructions for causing a computer system to design or simulate a circuit, the circuit comprising:
 circuit logic;   one or more scan chains coupled to the circuit logic, the one or more scan chains comprising scan cells operable in at least a scan mode and an operational mode; and   test logic coupled to a scan path of at least two of the scan cells, the test logic being configured to load the at least two of the scan cells with either a fixed value or a pseudo-random value while the scan cells are operating in the scan mode.   
     
     
         42 . The one or more computer-readable media of  claim 41 , wherein the test logic of the circuit is not directly coupled to the circuit logic. 
     
     
         43 . The one or more computer-readable media of  claim 41 , wherein the circuit further comprises a pseudo-random pattern generator coupled to the test logic, the pseudo-random pattern generator producing the pseudo-random value. 
     
     
         44 . The one or more computer-readable media of  claim 43 , wherein the pseudo-random pattern generator is a linear feedback shift register (LFSR). 
     
     
         45 . The one or more computer-readable media of  claim 41 , wherein the circuit further comprises a phase decoder coupled to the test logic, the phase decoder at least partially producing the fixed value. 
     
     
         46 . The one or more computer-readable media of  claim 45 , wherein the circuit further comprises a shift counter having an output signal that is logically coupled with an output signal of the phase decoder, the shift counter being configured to control when the fixed value is loaded by the test logic into the at least two of the scan cells. 
     
     
         47 . The one or more computer-readable media, of  claim 46 , wherein the shift counter is configured to load the fixed value during a last shift cycle of the scan mode. 
     
     
         48 . The one or more computer-readable media of  claim 41 , wherein the circuit further comprises an observation point in the circuit logic, the value at the observation point being indicative of the presence of a fault whose value does not otherwise propagate to circuit logic outputs. 
     
     
         49 . One or more computer-readable media storing computer-readable design information for a circuit, the circuit comprising:
 circuit logic;   one or more scan chains coupled to the circuit logic, the one or more scan chains comprising scan cells operable in at least a scan mode and an operational mode; and   test logic coupled to a scan path of at least two of the scan cells, the test logic being configured to load the at least two of the scan cells with either a fixed value or a pseudo-random value while the scan cells are operating in the scan mode.   
     
     
         50 . The one or more computer-readable media of  claim 49 , wherein the test logic is not directly coupled to the circuit logic. 
     
     
         51 . The one or more computer-readable media of  claim 49 , wherein the circuit further comprises pseudo-random pattern generator coupled to the test logic, the pseudo-random pattern generator producing the pseudo-random value. 
     
     
         52 . The one or more computer-readable media of  claim 51 , wherein the pseudo-random pattern generator is a linear feedback shift register (LFSR). 
     
     
         53 . The one or more computer-readable media of  claim 49 , wherein the circuit further comprises a phase decoder coupled to the test logic, the phase decoder at least partially producing the fixed value. 
     
     
         54 . The one or more computer-readable media of  claim 53 , wherein the circuit further comprises a shift counter having an output signal that is logically coupled with an output signal of the phase decoder, the shift counter being configured to control when the fixed value is loaded by the test logic into the at least two of the scan cells. 
     
     
         55 . The one or more computer-readable media of  claim 54 , wherein the shift counter is configured to load the fixed value during a last shift cycle of the scan mode. 
     
     
         56 . The one or more computer-readable media of  claim 49 , wherein the circuit further comprises an observation point in the circuit logic, the value at the observation point being indicative of the presence of a fault whose value does not otherwise propagate to circuit logic outputs.