Inventor · disambiguated record
Catherine B. Labelle
Also filed as: LABELLE CATHERINE · LABELLE CATHERINE B
23 granted patents·6 pending applications·149 citations·filing 2002–2018
94Inventor score
Files withGLOBALFOUNDRIES INC12ADVANCED MICRO DEVICES INC5BONSER DOUGLAS2IBM2ADVANCED MICRO DEVICES INC AMD1
Top patents by PatentIndex Score
29 records- 0198US9911619B1Fin cut with alternating two color fin hardmaskGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 6, 2018·24 cites·19 claims
- 0297US9761495B1Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·24 cites·20 claims
- 0395US9722024B1Formation of semiconductor structures employing selective removal of finsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 1, 2017·12 cites·16 claims
- 0492US9779960B2Hybrid fin cutting processes for FinFET semiconductor devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 3, 2017·9 cites·28 claims
- 0590US9431539B2Dual-strained nanowire and FinFET devices with dielectric isolationGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 30, 2016·11 cites·13 claims
- 0690US7049209B1De-fluorination of wafer surface and related structureIBM·Filed 2005·Granted May 23, 2006·16 cites·18 claims
- 0789US8174055B2Formation of FinFET gate spacerBONSER DOUGLAS·Filed 2010·Granted May 8, 2012·12 cites·12 claims
- 0886US9184263B2Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 10, 2015·7 cites·20 claims
- 0983US9837268B2Raised fin structures and methods of fabricationGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 5, 2017·3 cites·19 claims
- 1078US9391140B2Raised fin structures and methods of fabricationGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 12, 2016·3 cites·20 claims
- 1175US8932961B2Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesMEHTA SOHAN·Filed 2012·Granted Jan 13, 2015·5 cites·4 claims
- 1270US6982043B1Scatterometry with grating to observe resist removal rate during etchADVANCED MICRO DEVICES INC·Filed 2003·Granted Jan 3, 2006·13 cites·28 claims
- 1368US9881842B1Wimpy and nominal semiconductor device structures for vertical finFETsIBM·Filed 2017·Granted Jan 30, 2018·1 cites·20 claims
- 1467US8525234B2Formation of FinFET gate spacerBONSER DOUGLAS·Filed 2012·Granted Sep 3, 2013·2 cites·20 claims
- 1557US9064848B2ARC residue-free etchingGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jun 23, 2015·0 cites·16 claims
- 1653US6746973B1Effect of substrate surface treatment on 193 NM resist processingADVANCED MICRO DEVICES INC·Filed 2002·Granted Jun 8, 2004·4 cites·29 claims
- 1752US6793765B1Situ monitoring of microloading using scatterometry with variable pitch gratingsADVANCED MICRO DEVICES INC·Filed 2002·Granted Sep 21, 2004·3 cites·29 claims
- 1852US2015050811A1Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1949US10199479B2Methods of forming a gate cap layer above a replacement gate structureGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 5, 2019·0 cites·13 claims
- 2049US8901006B2ARC residue-free etchingHU XIANG·Filed 2011·Granted Dec 2, 2014·0 cites·10 claims
- 2149US2010267237A1Methods for fabricating finfet semiconductor devices using ashable sacrificial mandrelsADVANCED MICRO DEVICES INC·Filed 2009·Application pending·0 cites
- 2244US11380581B2Interconnect structures of semiconductor devices having a via structure through an upper conductive lineGLOBALFOUNDRIES US INC·Filed 2018·Granted Jul 5, 2022·0 cites·9 claims
- 2342US2007072412A1Preventing damage to interlevel dielectricADVANCED MICRO DEVICES INC AMD·Filed 2005·Application pending·0 cites
- 2441US9548249B2Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 17, 2017·0 cites·20 claims
- 2541US8448103B2Manufacturing features of different depth by placement of viasARNOLD JOHN C·Filed 2011·Granted May 21, 2013·0 cites·20 claims
- 2641US2013181265A1Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap LayerGRASSHOFF GUNTER·Filed 2012·Application pending·0 cites
- 2740US9875905B2FinFET devices having fins with a tapered configuration and methods of fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 23, 2018·0 cites·19 claims
- 2836US2005101147A1Method for integrating a high-k gate dielectric in a transistor fabrication processADVANCED MICRO DEVICES INC·Filed 2003·Application pending·0 cites
- 2932US2013224944A1Methods for fabricating integrated circuits using tailored chamfered gate liner profilesKHANNA PUNEET·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Catherine B. Labelle files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →