Inventor · disambiguated record
Judson R. Holt
Also filed as: HOLT JUDSON · HOLT JUDSON R · HOLT JUDSON ROBERT
193 granted patents·37 pending applications·1,386 citations·filing 2004–2024
99Inventor score
Files withGLOBALFOUNDRIES US INC83IBM67GLOBALFOUNDRIES INC36ADAM THOMAS N5CHARTERED SEMICONDUCTOR MFG5
Top patents by PatentIndex Score
230 records- 0198US10163635B1Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related methodGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·26 cites·13 claims
- 0298US8217423B2Structure and method for mobility enhanced MOSFETs with unalloyed silicideLIU YAOCHENG·Filed 2007·Granted Jul 10, 2012·97 cites·8 claims
- 0398US7859013B2Metal oxide field effect transistor with a sharp haloIBM·Filed 2007·Granted Dec 28, 2010·100 cites·17 claims
- 0498US7595010B2Method for producing a doped nitride film, doped oxide film and other doped filmsIBM·Filed 2007·Granted Sep 29, 2009·57 cites·1 claims
- 0598US7361611B2Doped nitride film, doped oxide film and other doped filmsIBM·Filed 2006·Granted Apr 22, 2008·55 cites·14 claims
- 0697US7002214B1Ultra-thin body super-steep retrograde well (SSRW) FET devicesIBM·Filed 2004·Granted Feb 21, 2006·160 cites·20 claims
- 0796US11803009B2Photonics structures having a locally-thickened dielectric layerGLOBALFOUNDRIES US INC·Filed 2022·Granted Oct 31, 2023·4 cites·20 claims
- 0896US11145725B2Heterojunction bipolar transistorGLOBALFOUNDRIES US INC·Filed 2020·Granted Oct 12, 2021·4 cites·20 claims
- 0996US9812453B1Self-aligned sacrificial epitaxial capping for trench silicideGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 7, 2017·22 cites·14 claims
- 1096US7718500B2Formation of raised source/drain structures in NFET with embedded SiGe in PFETCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted May 18, 2010·53 cites·22 claims
- 1196US7071103B2Chemical treatment to retard diffusion in a semiconductor overlayerIBM·Filed 2004·Granted Jul 4, 2006·120 cites·25 claims
- 1295US8017487B2Method to control source/drain stressor profiles for stress engineeringGLOBALFOUNDRIES SG PTE LTD·Filed 2006·Granted Sep 13, 2011·37 cites·21 claims
- 1395US7989298B1Transistor having V-shaped embedded stressorIBM·Filed 2010·Granted Aug 2, 2011·27 cites·20 claims
- 1495US7381623B1Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performanceIBM·Filed 2007·Granted Jun 3, 2008·31 cites·16 claims
- 1595US7001844B2Material for contact etch layer to enhance device performanceIBM·Filed 2004·Granted Feb 21, 2006·74 cites·35 claims
- 1694US11888031B2Fin-based lateral bipolar junction transistor and methodGLOBALFOUNDRIES US INC·Filed 2021·Granted Jan 30, 2024·2 cites·16 claims
- 1794US11843044B2Bipolar transistor structure on semiconductor fin and methods to form sameGLOBALFOUNDRIES US INC·Filed 2022·Granted Dec 12, 2023·2 cites·20 claims
- 1894US9627480B2Junction butting structure using nonuniform trench shapeGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 18, 2017·13 cites·11 claims
- 1994US9577100B2FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regionsGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 21, 2017·17 cites·13 claims
- 2094US9287264B1Epitaxially grown silicon germanium channel FinFET with silicon underlayerGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 15, 2016·15 cites·12 claims
- 2194US9034741B2Halo region formation by epitaxial growthIBM·Filed 2013·Granted May 19, 2015·15 cites·20 claims
- 2294US8492234B2Field effect transistor deviceCHAN KEVIN K·Filed 2010·Granted Jul 23, 2013·16 cites·12 claims
- 2393US11063139B2Heterojunction bipolar transistors with airgap isolationGLOBALFOUNDRIES US INC·Filed 2020·Granted Jul 13, 2021·3 cites·20 claims
- 2493US10396078B2Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·9 cites·16 claims
- 2593US10020307B1Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 10, 2018·9 cites·11 claims
- 2693US9443940B1Defect reduction with rotated double aspect ratio trappingIBM·Filed 2015·Granted Sep 13, 2016·9 cites·18 claims
- 2793US8642434B2Structure and method for mobility enhanced MOSFETS with unalloyed silicideLIU YAOCHENG·Filed 2012·Granted Feb 4, 2014·14 cites·14 claims
- 2893US8450775B2Method to control source/drain stressor profiles for stress engineeringCHONG YUNG FU·Filed 2011·Granted May 28, 2013·18 cites·20 claims
- 2992US11977258B1Structure with substrate-embedded arrow waveguide and methodGLOBALFOUNDRIES US INC·Filed 2022·Granted May 7, 2024·2 cites·20 claims
- 3092US8361859B2Stressed transistor with improved metastabilityIBM·Filed 2010·Granted Jan 29, 2013·13 cites·15 claims
- 3192US7947546B2Implant damage control by in-situ C doping during SiGe epitaxy for device applicationsCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted May 24, 2011·17 cites·52 claims
- 3291US10557779B2Semiconductor manufactured nano-structures for microbe or virus trapping or destructionIBM·Filed 2016·Granted Feb 11, 2020·4 cites·6 claims
- 3391US8575655B2Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineeringBEDELL STEPHEN W·Filed 2012·Granted Nov 5, 2013·9 cites·19 claims
- 3491US7572712B2Method to form selective strained Si using lateral epitaxyCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Aug 11, 2009·19 cites·32 claims
- 3591US7388278B2High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methodsIBM·Filed 2005·Granted Jun 17, 2008·33 cites·22 claims
- 3690US10043893B1Post gate silicon germanium channel condensation and method for producing the sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 7, 2018·5 cites·5 claims
- 3790US8288825B2Formation of raised source/drain structures in NFET with embedded SiGe in PFETCHONG YUNG FU·Filed 2010·Granted Oct 16, 2012·13 cites·24 claims
- 3889US11199672B1Multiple waveguide coupling to one or more photodetectorsGLOBALFOUNDRIES US INC·Filed 2020·Granted Dec 14, 2021·2 cites·20 claims
- 3989US9349864B1Methods for selectively forming a layer of increased dopant concentrationGLOBALFOUNDRIES INC·Filed 2015·Granted May 24, 2016·7 cites·20 claims
- 4089US7485524B2MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the sameIBM·Filed 2006·Granted Feb 3, 2009·17 cites·1 claims
- 4188US7482656B2Method and structure to form self-aligned selective-SOIIBM·Filed 2006·Granted Jan 27, 2009·15 cites·18 claims
- 4287US11710771B2Non-self-aligned lateral bipolar junction transistorsGLOBALFOUNDRIES US INC·Filed 2021·Granted Jul 25, 2023·1 cites·20 claims
- 4387US10393635B2Semiconductor manufactured nano-structures for microbe or virus trapping or destructionIBM·Filed 2016·Granted Aug 27, 2019·2 cites·5 claims
- 4487US10049942B2Asymmetric semiconductor device and method of forming sameGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 14, 2018·5 cites·11 claims
- 4587US9123826B1Single crystal source-drain merged by polycrystalline materialIBM·Filed 2014·Granted Sep 1, 2015·8 cites·20 claims
- 4687US8940595B2Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levelsIBM·Filed 2013·Granted Jan 27, 2015·8 cites·20 claims
- 4787US7772676B2Strained semiconductor device and method of making sameINFINEON TECHNOLOGIES AG·Filed 2006·Granted Aug 10, 2010·13 cites·17 claims
- 4886US8299535B2Delta monolayer dopants epitaxy for embedded source/drain silicideCHAN KEVIN K·Filed 2010·Granted Oct 30, 2012·9 cites·20 claims
- 4986US8232172B2Stress enhanced transistor devices and methods of makingADAM THOMAS N·Filed 2011·Granted Jul 31, 2012·6 cites·6 claims
- 5085US11652142B2Lateral bipolar junction transistors having an emitter extension and a halo regionGLOBALFOUNDRIES US INC·Filed 2021·Granted May 16, 2023·1 cites·20 claims
Showing the top 50 of 230 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →